From: Thomas Garnier Subject: Re: x86: PIE support and option to extend KASLR randomization Date: Fri, 25 Aug 2017 08:35:49 -0700 Message-ID: References: <20170810172615.51965-1-thgarnie@google.com> <20170811124127.kkb5pnkljz4umxuj@gmail.com> <20170815075609.mmzbfwritjzvrpsn@gmail.com> <20170816151235.oamkdva6cwpc4cex@gmail.com> <20170817080920.5ljlkktngw2cisfg@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Cc: Ingo Molnar , Herbert Xu , "David S . Miller" , Thomas Gleixner , Ingo Molnar , "H . Peter Anvin" , Peter Zijlstra , Josh Poimboeuf , Arnd Bergmann , Matthias Kaehlcke , Boris Ostrovsky , Juergen Gross , Paolo Bonzini , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , Joerg Roedel , Tom Lendacky , Andy Lutomirski , Borislav Petkov , Brian Gerst , "Kirill A . Shutemov" , "Rafael J . Wysocki" , Len Brown , Pavel Machek , Tejun H To: Linus Torvalds Return-path: List-Post: List-Help: List-Unsubscribe: List-Subscribe: In-Reply-To: List-Id: linux-crypto.vger.kernel.org On Thu, Aug 24, 2017 at 2:42 PM, Linus Torvalds wrote: > > On Thu, Aug 24, 2017 at 2:13 PM, Thomas Garnier wrote: > > > > My original performance testing was done with an Ubuntu generic > > configuration. This configuration has the CONFIG_FUNCTION_TRACER > > option which was incompatible with PIE. The tracer failed to replace > > the __fentry__ call by a nop slide on each traceable function because > > the instruction was not the one expected. If PIE is enabled, gcc > > generates a difference call instruction based on the GOT without > > checking the visibility options (basically call *__fentry__@GOTPCREL). > > Gah. > > Don't we actually have *more* address bits for randomization at the > low end, rather than getting rid of -mcmodel=kernel? We have but I think we use most of it for potential modules and the fixmap but it is not that big. The increase in range from 1G to 3G is just an example and a way to ensure PIE work as expected. The long term goal is being able to put the kernel where we want in memory, randomizing the position and the order of almost all memory sections. That would be valuable against BTB attack [1] for example where randomization on the low 32-bit is ineffective. [1] https://github.com/felixwilhelm/mario_baslr > > Has anybody looked at just moving kernel text by smaller values than > the page size? Yeah, yeah, the kernel has several sections that need > page alignment, but I think we could relocate normal text by just the > cacheline size, and that sounds like it would give several bits of > randomness with little downside. I didn't look into it. There is value in it depending on performance impact. I think both PIE and lower grain randomization would be useful. > > Or has somebody already looked at it and I just missed it? > > Linus -- Thomas