From:   Kalyani Akula <kalyania@xilinx.com>
To:     Corentin Labbe <clabbe.montjoie@gmail.com>
CC:     "herbert@gondor.apana.org.au" <herbert@gondor.apana.org.au>,
        "davem@davemloft.net" <davem@davemloft.net>,
        "linux-crypto@vger.kernel.org" <linux-crypto@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [RFC PATCH V2 3/4] crypto: Add Xilinx SHA3 driver
Thread-Topic: [RFC PATCH V2 3/4] crypto: Add Xilinx SHA3 driver
Thread-Index: AQHUp/1sQxJENQki50GijbSiY6ngFqWoiP+AgJ+wkOA=
Date:   Mon, 22 Apr 2019 06:47:15 +0000
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Hi Corentin,

Sorry for the delayed response.
Please find my responses inline.

> -----Original Message-----
> From: Corentin Labbe <clabbe.montjoie@gmail.com>
> Sent: Thursday, January 10, 2019 7:28 PM
> To: Kalyani Akula <kalyania@xilinx.com>
> Cc: herbert@gondor.apana.org.au; davem@davemloft.net; linux-
> crypto@vger.kernel.org; linux-kernel@vger.kernel.org; Kalyani Akula
> <kalyania@xilinx.com>; Sarat Chand Savitala <saratcha@xilinx.com>
> Subject: Re: [RFC PATCH V2 3/4] crypto: Add Xilinx SHA3 driver
>=20
> On Wed, Jan 09, 2019 at 02:56:24PM +0530, Kalyani Akula wrote:
> > This patch adds SHA3 driver support for the Xilinx ZynqMP SoC.
> >
> > Signed-off-by: Kalyani Akula <kalyani.akula@xilinx.com>
> > ---
> >  drivers/crypto/Kconfig      |   10 ++
> >  drivers/crypto/Makefile     |    1 +
> >  drivers/crypto/zynqmp-sha.c |  305
> > +++++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 316 insertions(+), 0 deletions(-)  create mode
> > 100644 drivers/crypto/zynqmp-sha.c
>=20
> Hello
>=20
> I have some comment below
>=20
> > +static int zynqmp_sha_update(struct ahash_request *req) {
> > +	const struct zynqmp_eemi_ops *eemi_ops =3D
> zynqmp_pm_get_eemi_ops();
> > +	struct zynqmp_sha_ctx *tctx =3D crypto_tfm_ctx(req->base.tfm);
> > +	struct zynqmp_sha_dev *dd =3D tctx->dd;
> > +	size_t dma_size =3D req->nbytes;
> > +	dma_addr_t dma_addr;
> > +	char *kbuf;
> > +	int ret;
> > +
> > +	if (!req->nbytes)
> > +		return 0;
> > +
> > +	if (!eemi_ops || !eemi_ops->sha_hash)
> > +		return -ENOTSUPP;
> > +
> > +	kbuf =3D dma_alloc_coherent(dd->dev, dma_size, &dma_addr,
> GFP_KERNEL);
> > +	if (!kbuf)
> > +		return -ENOMEM;
> > +
> > +	scatterwalk_map_and_copy(kbuf, req->src, 0, req->nbytes, 0);
> > +	 __flush_cache_user_range((unsigned long)kbuf,
> > +				  (unsigned long)kbuf + dma_size);
>=20
> Since kbuf is in dma coherent memory, I dont understand why do you flush
> cache.
[kalyani] Agree, not required will fix in next version.
>=20
> > +	ret =3D eemi_ops->sha_hash(dma_addr, req->nbytes,
> ZYNQMP_SHA3_UPDATE);
> > +	dma_free_coherent(dd->dev, dma_size, kbuf, dma_addr);
>=20
> Since your update function does not return/write any result, I suppose th=
at
> the resulat is kept in hardware, so what happen if two hash process happe=
n
> in parallel ?
[kalyani] yes, the result will be stored in SHA3 engine.
Firmware don't have the support to process 2 hash requests in parallel usin=
g IPI
> Furthermore, how do you have tested import/export function ?
> Anyway, I am sure they are totally buggy.
>=20
[kalyani] I will verify and fix in the next version
> > +
> > +	return ret;
> > +}
> > +
> > +static int zynqmp_sha_final(struct ahash_request *req) {
> > +	const struct zynqmp_eemi_ops *eemi_ops =3D
> zynqmp_pm_get_eemi_ops();
> > +	struct zynqmp_sha_ctx *tctx =3D crypto_tfm_ctx(req->base.tfm);
> > +	struct zynqmp_sha_dev *dd =3D tctx->dd;
> > +	size_t dma_size =3D SHA384_DIGEST_SIZE;
> > +	dma_addr_t dma_addr;
> > +	char *kbuf;
> > +	int ret;
> > +
> > +	if (!eemi_ops || !eemi_ops->sha_hash)
> > +		return -ENOTSUPP;
>=20
> You can do this check at probe time.
[kalyani] Yes, will fix in next version
>=20
> > +static int zynqmp_sha_finup(struct ahash_request *req) {
> > +	zynqmp_sha_update(req);
> > +	zynqmp_sha_final(req);
> > +
> > +	return 0;
> > +}
> > +
> > +static int zynqmp_sha_digest(struct ahash_request *req) {
> > +	zynqmp_sha_init(req);
> > +	zynqmp_sha_update(req);
> > +	zynqmp_sha_final(req);
> > +
> > +	return 0;
> > +}
>=20
> So you ignore the return value of
> zynqmp_sha_init/zynqmp_sha_update/zynqmp_sha_final().
>=20
> > +static int zynqmp_sha_probe(struct platform_device *pdev) {
> > +	struct zynqmp_sha_dev *sha_dd;
> > +	struct device *dev =3D &pdev->dev;
> > +	int err;
> > +
> > +	sha_dd =3D devm_kzalloc(&pdev->dev, sizeof(*sha_dd),
> GFP_KERNEL);
> > +	if (!sha_dd)
> > +		return -ENOMEM;
> > +
> > +	sha_dd->dev =3D dev;
> > +	platform_set_drvdata(pdev, sha_dd);
> > +	INIT_LIST_HEAD(&sha_dd->list);
> > +	spin_lock_init(&sha_dd->lock);
> > +	crypto_init_queue(&sha_dd->queue,
> ZYNQMP_SHA_QUEUE_LENGTH);
>=20
> As already said in my last review, why init the queue if you do not use i=
t ?
>=20
>=20
> > +	spin_lock(&zynqmp_sha.lock);
> > +	list_add_tail(&sha_dd->list, &zynqmp_sha.dev_list);
> > +	spin_unlock(&zynqmp_sha.lock);
>=20
> Why do you maintain a device list ?
> Clearly your current driver support only one hardware instance.
[kalyani] True, driver support only one HW instance , will fix in the next =
version

Regards,
kalyani
>=20
> Regards