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From:   Horia Geanta <horia.geanta@nxp.com>
To:     Herbert Xu <herbert@gondor.apana.org.au>
CC:     Ard Biesheuvel <ard.biesheuvel@linaro.org>,
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        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        dl-linux-imx <linux-imx@nxp.com>
Subject: Re: [PATCH] crypto: gcm - fix cacheline sharing
Thread-Topic: [PATCH] crypto: gcm - fix cacheline sharing
Thread-Index: AQHVFkF+dOvdDzZqYUSH856vNqfARw==
Date:   Fri, 31 May 2019 05:22:50 +0000
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On 5/30/2019 4:26 PM, Herbert Xu wrote:=0A=
> On Thu, May 30, 2019 at 01:18:34PM +0000, Horia Geanta wrote:=0A=
>>=0A=
>> I guess there are only two options:=0A=
>> -either cache line sharing is avoided OR=0A=
>> -users need to be *aware* they are sharing the cache line and some rules=
 /=0A=
>> assumptions are in place on how to safely work on the data=0A=
> =0A=
> No there is a third option and it's very simple:=0A=
> =0A=
I see this as the 2nd option.=0A=
=0A=
> You must only access the virtual addresses given to you before DMA=0A=
> mapping or after DMA unmapping.=0A=
> =0A=
Unless it's clearly defined *which* virtual addresses mustn't be accessed,=
=0A=
things won't work properly.=0A=
In theory, any two objects could share a cache line. We can't just stop all=
=0A=
memory accesses from CPU while a peripheral is busy.=0A=
=0A=
Thanks,=0A=
Horia=0A=