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From:   Leonard Crestez <leonard.crestez@nxp.com>
To:     Andrey Smirnov <andrew.smirnov@gmail.com>,
        "linux-crypto@vger.kernel.org" <linux-crypto@vger.kernel.org>,
        Horia Geanta <horia.geanta@nxp.com>
CC:     Chris Spencer <christopher.spencer@sea.co.uk>,
        Aymen Sghaier <aymen.sghaier@nxp.com>,
        Franck Lenormand <franck.lenormand@nxp.com>,
        Cory Tusar <cory.tusar@zii.aero>,
        Chris Healy <cphealy@gmail.com>,
        Lucas Stach <l.stach@pengutronix.de>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Iuliana Prodan <iuliana.prodan@nxp.com>
Subject: Re: [PATCH v3 2/5] crypto: caam - correct DMA address size for the
 i.MX8
Thread-Topic: [PATCH v3 2/5] crypto: caam - correct DMA address size for the
 i.MX8
Thread-Index: AQHVJSZIVXANdmo1E06O+7eMXYofbw==
Date:   Mon, 17 Jun 2019 19:24:25 +0000
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References: <20190617160339.29179-1-andrew.smirnov@gmail.com>
 <20190617160339.29179-3-andrew.smirnov@gmail.com>
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On 6/17/2019 7:04 PM, Andrey Smirnov wrote:=0A=
> From: Chris Spencer <christopher.spencer@sea.co.uk>=0A=
> =0A=
> The i.MX8 is arm64, but its CAAM DMA address size is 32-bits.=0A=
=0A=
> +/*=0A=
> + * On i.MX8 boards the arch is arm64 but the CAAM dma address size is=0A=
> + * 32 bits on 8MQ and 36 bits on 8QM and 8QXP.=0A=
> + * For 8QM and 8QXP there is a configurable field PS called pointer size=
=0A=
> + * in the MCFGR register to switch between 32 and 64 (default 32)=0A=
> + * But this register is only accessible by the SECO and is left to its=
=0A=
> + * default value.=0A=
> + * Here we set the CAAM dma address size to 32 bits for all i.MX8=0A=
> + */=0A=
> +#if defined(CONFIG_ARM64) && defined(CONFIG_ARCH_MXC)=0A=
> +#define caam_dma_addr_t u32=0A=
> +#else=0A=
> +#define caam_dma_addr_t dma_addr_t=0A=
> +#endif=0A=
=0A=
Wait, doesn't this break Layerscape? Support for multiple SOC families =0A=
can be enabled at the same time and it is something that we actually =0A=
want to support.=0A=
=0A=
--=0A=
Regards,=0A=
Leonard=0A=