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McKenney" , Peter Zijlstra , linux-arch@vger.kernel.org, linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Mathias Krause Subject: Re: [PATCH] padata: Replace delayed timer with immediate workqueue in padata_reorder Message-ID: <20190719142113.ixalfoikevwnhvaq@ca-dmjordan1.us.oracle.com> References: <20190716163253.24377-1-daniel.m.jordan@oracle.com> <20190717111147.t776zlyhdqyl5dhc@gondor.apana.org.au> <20190717232136.pboms73sqf6fdzic@ca-dmjordan1.us.oracle.com> <20190718033008.wle67s7esg27mrtz@gondor.apana.org.au> <20190718142515.teinr4da3gps5r7a@ca-dmjordan1.us.oracle.com> <20190718144950.yc6sambgdsz7vrvq@gondor.apana.org.au> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190718144950.yc6sambgdsz7vrvq@gondor.apana.org.au> User-Agent: NeoMutt/20180323-268-5a959c X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9322 signatures=668688 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=526 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1907190160 X-Proofpoint-Virus-Version: vendor=nai engine=6000 definitions=9322 signatures=668688 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=578 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1907190160 Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org On Thu, Jul 18, 2019 at 10:49:50PM +0800, Herbert Xu wrote: > On Thu, Jul 18, 2019 at 10:25:15AM -0400, Daniel Jordan wrote: > > > > Which memory barrier do you mean? I think you're referring to the one that > > atomic_inc might provide? If so, the memory model maintainers can correct me > > here, but my understanding is that RMW atomic ops that don't return values are > > unordered, so switching the lines has no effect. > > > > Besides, the smp_mb__after_atomic is what orders the list insertion with the > > trylock of pd->lock. > > The primitive smp_mb__after_atomic only provides a barrier when > used in conjunction with atomic_inc (and similar atomic ops). > > The actual barrier may either be in smp_mb__after_atomic or the > atomic op itself (which is the case on x86). Since we need the > barrier to occur after the list insertion we must move both of > these after the list_add_tail. Yes, my mistake! Thanks for clarifying that.