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From:   Iuliana Prodan <iuliana.prodan@nxp.com>
To:     Herbert Xu <herbert@gondor.apana.org.au>,
        Andrey Smirnov <andrew.smirnov@gmail.com>
CC:     "linux-crypto@vger.kernel.org" <linux-crypto@vger.kernel.org>,
        "christopher.spencer@sea.co.uk" <christopher.spencer@sea.co.uk>,
        "cory.tusar@zii.aero" <cory.tusar@zii.aero>,
        "cphealy@gmail.com" <cphealy@gmail.com>,
        "l.stach@pengutronix.de" <l.stach@pengutronix.de>,
        Horia Geanta <horia.geanta@nxp.com>,
        Aymen Sghaier <aymen.sghaier@nxp.com>,
        Leonard Crestez <leonard.crestez@nxp.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v8 00/16] crypto: caam - Add i.MX8MQ support
Thread-Topic: [PATCH v8 00/16] crypto: caam - Add i.MX8MQ support
Thread-Index: AQHVV5VB3CgVSzdtsUuKFBe5Nr//dA==
Date:   Fri, 30 Aug 2019 09:15:12 +0000
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References: <20190830082320.GA8729@gondor.apana.org.au>
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On 8/30/2019 11:23 AM, Herbert Xu wrote:=0A=
> Andrey Smirnov <andrew.smirnov@gmail.com> wrote:=0A=
>> Everyone:=0A=
>>=0A=
>> Picking up where Chris left off (I chatted with him privately=0A=
>> beforehead), this series adds support for i.MX8MQ to CAAM driver. Just=
=0A=
>> like [v1], this series is i.MX8MQ only.=0A=
>>=0A=
>> Feedback is welcome!=0A=
>> Thanks,=0A=
>> Andrey Smirnov=0A=
>>=0A=
>> Changes since [v7]:=0A=
>>=0A=
>>   - Series rebase on latest cryptodev-2.6 (198429631a85)=0A=
>>=0A=
>>   - "crypto: caam - force DMA address to 32-bit on 64-bit i.MX SoCs"=0A=
>>     converted to use CTPR and MCFGR to determine CAAM pointer width=0A=
>>     and renamed to "crypto: caam - select DMA address size at runtime"=
=0A=
>>=0A=
>>   - Patch adding corresponding DT node added to the series=0A=
>>=0A=
>> Changes since [v6]:=0A=
>>=0A=
>>   - Fixed build problems in "crypto: caam - make CAAM_PTR_SZ dynamic"=0A=
>>=0A=
>>   - Collected Reviewied-by from Horia=0A=
>>=0A=
>>   - "crypto: caam - force DMA address to 32-bit on 64-bit i.MX SoCs"=0A=
>>     is changed to check 'caam_ptr_sz' instead of using 'caam_imx'=0A=
>>     =0A=
>>   - Incorporated feedback for "crypto: caam - request JR IRQ as the=0A=
>>     last step" and "crypto: caam - simplfy clock initialization"=0A=
>>=0A=
>> Changes since [v5]:=0A=
>>=0A=
>>   - Hunk replacing sizeof(*jrp->inpring) to SIZEOF_JR_INPENTRY in=0A=
>>     "crypto: caam - don't hardcode inpentry size", lost in [v5], is=0A=
>>     back=0A=
>>=0A=
>>   - Collected Tested-by from Iuliana=0A=
>>=0A=
>> Changes since [v4]:=0A=
>>=0A=
>>   - Fixed missing sentinel element in "crypto: caam - simplfy clock=0A=
>>     initialization"=0A=
>>     =0A=
>>   - Squashed all of the devers related patches into a single one and=0A=
>>     converted IRQ allocation to use devres while at it=0A=
>>=0A=
>>   - Added "crypto: caam - request JR IRQ as the last step" as=0A=
>>     discussed=0A=
>>=0A=
>> Changes since [v3]:=0A=
>>=0A=
>>   - Patchset changed to select DMA size at runtime in order to enable=0A=
>>     support for both i.MX8MQ and Layerscape at the same time. I only=0A=
>>     tested the patches on i.MX6,7 and 8MQ, since I don't have access=0A=
>>     to any of the Layerscape HW. Any help in that regard would be=0A=
>>     appareciated.=0A=
>>=0A=
>>   - Bulk clocks and their number are now stored as a part of struct=0A=
>>     caam_drv_private to simplify allocation and cleanup code (no=0A=
>>     special context needed)=0A=
>>     =0A=
>>   - Renamed 'soc_attr' -> 'imx_soc_match' for clarity=0A=
>>=0A=
>> Changes since [v2]:=0A=
>>=0A=
>>   - Dropped "crypto: caam - do not initialise clocks on the i.MX8" and=
=0A=
>>     replaced it with "crypto: caam - simplfy clock initialization" and=
=0A=
>>     "crypto: caam - add clock entry for i.MX8MQ"=0A=
>>=0A=
>>=0A=
>> Changes since [v1]=0A=
>>=0A=
>>   - Series reworked to continue using register based interface for=0A=
>>     queueing RNG initialization job, dropping "crypto: caam - use job=0A=
>>     ring for RNG instantiation instead of DECO"=0A=
>>=0A=
>>   - Added a patch to share DMA mask selection code=0A=
>>=0A=
>>   - Added missing Signed-off-by for authors of original NXP tree=0A=
>>     commits that this sereis is based on=0A=
>>=0A=
>> [v7] lore.kernel.org/r/20190812200739.30389-1-andrew.smirnov@gmail.com=
=0A=
>> [v6] lore.kernel.org/r/20190717152458.22337-1-andrew.smirnov@gmail.com=
=0A=
>> [v5] lore.kernel.org/r/20190715201942.17309-1-andrew.smirnov@gmail.com=
=0A=
>> [v4] lore.kernel.org/r/20190703081327.17505-1-andrew.smirnov@gmail.com=
=0A=
>> [v3] lore.kernel.org/r/20190617160339.29179-1-andrew.smirnov@gmail.com=
=0A=
>> [v2] lore.kernel.org/r/20190607200225.21419-1-andrew.smirnov@gmail.com=
=0A=
>> [v1] https://eur01.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2=
Fpatchwork.kernel.org%2Fcover%2F10825625%2F&amp;data=3D02%7C01%7Ciuliana.pr=
odan%40nxp.com%7C33d82b783fe44b7397a108d72d2361d7%7C686ea1d3bc2b4c6fa92cd99=
c5c301635%7C0%7C0%7C637027502298978288&amp;sdata=3DTc%2FSuS60cL8%2FLisYBtfa=
rPAVmcx7ITpNgaiLMq5YLIs%3D&amp;reserved=3D0=0A=
>>=0A=
>> Andrey Smirnov (16):=0A=
>>   crypto: caam - move DMA mask selection into a function=0A=
>>   crypto: caam - simplfy clock initialization=0A=
>>   crypto: caam - convert caam_jr_init() to use devres=0A=
>>   crypto: caam - request JR IRQ as the last step=0A=
>>   crytpo: caam - make use of iowrite64*_hi_lo in wr_reg64=0A=
>>   crypto: caam - use ioread64*_hi_lo in rd_reg64=0A=
>>   crypto: caam - drop 64-bit only wr/rd_reg64()=0A=
>>   crypto: caam - share definition for MAX_SDLEN=0A=
>>   crypto: caam - make CAAM_PTR_SZ dynamic=0A=
>>   crypto: caam - move cpu_to_caam_dma() selection to runtime=0A=
>>   crypto: caam - drop explicit usage of struct jr_outentry=0A=
>>   crypto: caam - don't hardcode inpentry size=0A=
>>   crypto: caam - select DMA address size at runtime=0A=
>>   crypto: caam - always select job ring via RSR on i.MX8MQ=0A=
>>   crypto: caam - add clock entry for i.MX8MQ=0A=
>>   arm64: dts: imx8mq: Add CAAM node=0A=
>>=0A=
>> arch/arm64/boot/dts/freescale/imx8mq.dtsi |  30 +++=0A=
>> drivers/crypto/caam/caamalg.c             |   2 +-=0A=
>> drivers/crypto/caam/caamalg_qi2.h         |  27 ---=0A=
>> drivers/crypto/caam/caamhash.c            |   2 +-=0A=
>> drivers/crypto/caam/caampkc.c             |   8 +-=0A=
>> drivers/crypto/caam/caamrng.c             |   2 +-=0A=
>> drivers/crypto/caam/ctrl.c                | 221 ++++++++++------------=
=0A=
>> drivers/crypto/caam/desc_constr.h         |  47 ++++-=0A=
>> drivers/crypto/caam/error.c               |   3 +=0A=
>> drivers/crypto/caam/intern.h              |  32 +++-=0A=
>> drivers/crypto/caam/jr.c                  |  93 +++------=0A=
>> drivers/crypto/caam/pdb.h                 |  16 +-=0A=
>> drivers/crypto/caam/pkc_desc.c            |   8 +-=0A=
>> drivers/crypto/caam/qi.h                  |  26 ---=0A=
>> drivers/crypto/caam/regs.h                | 140 ++++++++++----=0A=
>> 15 files changed, 359 insertions(+), 298 deletions(-)=0A=
> =0A=
> Patches 1-15 applied.  Thanks.=0A=
> =0A=
Hi Herbert,=0A=
=0A=
Can you, please, add, also, the device tree patch ("arm64: dts: imx8mq: =0A=
Add CAAM node") in cryptodev tree?=0A=
Unfortunately Shawn Guo wasn't cc-ed on this patch and, to have the =0A=
complete support for imx8mq, in kernel v5.4, we need the node in dts.=0A=
=0A=
Thank you,=0A=
Iulia=0A=