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[209.132.180.67]) by mx.google.com with ESMTP id f43si14887085edf.422.2019.09.11.11.32.11; Wed, 11 Sep 2019 11:32:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b="jmgDd6/9"; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729859AbfIKScD (ORCPT + 99 others); Wed, 11 Sep 2019 14:32:03 -0400 Received: from mail-wm1-f67.google.com ([209.85.128.67]:54628 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729867AbfIKScD (ORCPT ); Wed, 11 Sep 2019 14:32:03 -0400 Received: by mail-wm1-f67.google.com with SMTP id p7so4647875wmp.4; Wed, 11 Sep 2019 11:32:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=6Te7QE2Q2g9STJbNhhZtv5SiHSyMZyM+FEre3Dz6O8Y=; b=jmgDd6/90ZK/KSjOdrNqJAxGaDbwNjQJv5BWKzzKlM6LwUpEtBrZ4S/M6pY1Y2zwVV SYnUdgL2vXoRYvJP69g7kRU8ygDsin0HwQX37zUefUMQVvvH3BAdctndGQ6ajD6V9/p7 B1LcD9Q7jXCDeUw1PxdEbcIiApu7ZJyDqkv7hu7B4b4A8tl+7W7n43Ja8y2XVNmsXXPi 2JPPtO9FTxf2qhFuv126oXjMVF1OO2LnELKexrwxJc+me24+3CWUCeR0oF52zerphQst zBF8s+lLPpx4Eftb2S04xTlTUUEcd1SSmuWlDD040Yc/OoyaxfqGL0I2+/RiA08WTukU 7idQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=6Te7QE2Q2g9STJbNhhZtv5SiHSyMZyM+FEre3Dz6O8Y=; b=AvqMrVhdS+y4k2C+F5j8z4JWxoLuQ63V3BSHwamMbVV7UasN7S4lm5KuwJZ5+NEGDW 4jeTheYzQGcQXWOKsuc0Km+2I5hwTU8Qg+gkCpLC0uJ8NUmujgWs3E5ErSslV0jLAT67 sec5ORsNSD0vOMPDkSmhqizV6yP492n3zhXErfanD94eENa/tj4LLdqRGSzS7vdymQKE GXFh7JGCmdaRjyoxmyDXccC7l5iHa+UTgqdtNHaaqt9DyjujOU6KkudIMUQJ1OWb7Hn5 JxF4a24WXo3wOCoFc0jYIddhZDcu4C5AOSrhn1Pc9rYRdFLzJ/+Lbug7710/xZjWgF02 Ri4w== X-Gm-Message-State: APjAAAX1U2UPwYUFt3Gyx0A8KRZVZtkDqNouNaLI/VJs2nwBXlpSEQPi zz7IU+ylV2yYPQybjEDJKiI= X-Received: by 2002:a1c:5451:: with SMTP id p17mr5092099wmi.103.1568226721265; Wed, 11 Sep 2019 11:32:01 -0700 (PDT) Received: from Red ([2a01:cb1d:147:7200:2e56:dcff:fed2:c6d6]) by smtp.googlemail.com with ESMTPSA id i9sm5162622wmf.14.2019.09.11.11.31.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Sep 2019 11:32:00 -0700 (PDT) Date: Wed, 11 Sep 2019 20:31:58 +0200 From: Corentin Labbe To: Maxime Ripard Cc: davem@davemloft.net, herbert@gondor.apana.org.au, linux@armlinux.org.uk, mark.rutland@arm.com, robh+dt@kernel.org, wens@csie.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: Re: [PATCH 3/9] dt-bindings: crypto: Add DT bindings documentation for sun8i-ce Crypto Engine Message-ID: <20190911183158.GA8264@Red> References: <20190906184551.17858-1-clabbe.montjoie@gmail.com> <20190906184551.17858-4-clabbe.montjoie@gmail.com> <20190907040116.lib532o2eqt4qnvv@flea> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190907040116.lib532o2eqt4qnvv@flea> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org On Sat, Sep 07, 2019 at 07:01:16AM +0300, Maxime Ripard wrote: > On Fri, Sep 06, 2019 at 08:45:45PM +0200, Corentin Labbe wrote: > > This patch adds documentation for Device-Tree bindings for the > > Crypto Engine cryptographic accelerator driver. > > > > Signed-off-by: Corentin Labbe > > --- > > .../bindings/crypto/allwinner,sun8i-ce.yaml | 84 +++++++++++++++++++ > > 1 file changed, 84 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml > > > > diff --git a/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml b/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml [...] > > +else: > > + clocks: > > + items: > > + - description: Bus clock > > + - description: Module clock > > + > > + clock-names: > > + items: > > + - const: ahb > > + - const: mod > > + > > + resets: > > + maxItems: 1 > > + > > + reset-names: > > + const: ahb > > This prevents the usage of the additionalProperties property, which > you should really use. > > What you can do instead is moving the clocks and clock-names > description under properties, with a minItems of 2 and a maxItems of > 3. Then you can restrict the length of that property to either 2 or 3 > depending on the case here. > Hello I fail to do this. I do the following (keeped only clock stuff) properties: clocks: items: - description: Bus clock - description: Module clock - description: MBus clock clock-names: items: - const: ahb - const: mod - const: mbus if: properties: compatible: items: const: allwinner,sun50i-h6-crypto then: properties: clocks: minItems: 3 maxItems: 3 clock-names: minItems: 3 maxItems: 3 else: properties: clocks: minItems: 2 maxItems: 2 clock-names: minItems: 2 maxItems: 2 With this, the dtb_check keep complain that a64 have two short clocks. Regards