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Date:   Fri, 04 Oct 2019 15:15:24 +0000
Message-ID: <20191004151524.Horde.zXUzQP5eBQt7Ybx5I75Ig5X@www.vdorst.com>
From:   =?utf-8?b?UmVuw6k=?= van Dorst <opensource@vdorst.com>
To:     "Jason A. Donenfeld" <Jason@zx2c4.com>
Cc:     Ard Biesheuvel <ard.biesheuvel@linaro.org>,
        "open list:HARDWARE RANDOM NUMBER GENERATOR CORE" 
        <linux-crypto@vger.kernel.org>,
        Herbert Xu <herbert@gondor.apana.org.au>,
        David Miller <davem@davemloft.net>,
        Greg KH <gregkh@linuxfoundation.org>,
        Linus Torvalds <torvalds@linux-foundation.org>,
        Samuel Neves <sneves@dei.uc.pt>,
        Dan Carpenter <dan.carpenter@oracle.com>,
        Arnd Bergmann <arnd@arndb.de>,
        Eric Biggers <ebiggers@google.com>,
        Andy Lutomirski <luto@kernel.org>,
        Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
        Catalin Marinas <catalin.marinas@arm.com>,
        Martin Willi <martin@strongswan.org>,
        Peter Zijlstra <peterz@infradead.org>,
        Josh Poimboeuf <jpoimboe@redhat.com>
Subject: Re: [PATCH v2 05/20] crypto: mips/chacha - import accelerated 32r2
 code from Zinc
References: <20191002141713.31189-1-ard.biesheuvel@linaro.org>
 <20191002141713.31189-6-ard.biesheuvel@linaro.org>
 <20191004134644.GE112631@zx2c4.com>
 <CAKv+Gu_X9DBgUiPqcyJ2hOQqi_FEBVpHOr9uG1ZAh-RWv6-z9Q@mail.gmail.com>
 <CAHmME9ojUTysb2kHKbSWaR+2Qat3qF1cNrVtphu3V+C+P_g8yQ@mail.gmail.com>
In-Reply-To: <CAHmME9ojUTysb2kHKbSWaR+2Qat3qF1cNrVtphu3V+C+P_g8yQ@mail.gmail.com>
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Hi Jason,

Quoting "Jason A. Donenfeld" <Jason@zx2c4.com>:

> On Fri, Oct 4, 2019 at 4:44 PM Ard Biesheuvel  
> <ard.biesheuvel@linaro.org> wrote:
>> The round count is passed via the fifth function parameter, so it is
>> already on the stack. Reloading it for every block doesn't sound like
>> a huge deal to me.
>
> Please benchmark it to indicate that, if it really isn't a big deal. I
> recall finding that memory accesses on common mips32r2 commodity
> router hardware was extremely inefficient. The whole thing is designed
> to minimize memory accesses, which are the primary bottleneck on that
> platform.

I also think it isn't a big deal, but I shall benchmark it this weekend.
If I am correct a memory write will first put in cache. So if you read
it again and it is in cache it is very fast. 1 or 2 clockcycles.
Also the value isn't used directly after it is read.
So cpu don't have to stall on this read.

Greats,

René

>
> Seems like this thing might be best deferred for after this all lands.
> IOW, let's get this in with the 20 round original now, and later you
> can submit a change for the 12 round and René and I can spend time
> dusting off our test rigs and seeing which strategy works best. I very
> nearly tossed out a bunch of old router hardware last night when
> cleaning up. Glad I saved it!