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[213.99.162.212]) by smtp.gmail.com with ESMTPSA id j10sm51846wrx.30.2019.11.08.03.09.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 08 Nov 2019 03:10:00 -0800 (PST) Subject: Re: [PATCH v4 1/1] arm64: Implement archrandom.h for ARMv8.5-RNG To: Ard Biesheuvel Cc: linux-arm-kernel , "open list:HARDWARE RANDOM NUMBER GENERATOR CORE" , Mark Rutland References: <20191106141954.30657-1-rth@twiddle.net> <20191106141954.30657-2-rth@twiddle.net> From: Richard Henderson Openpgp: preference=signencrypt Message-ID: <23ce309b-1561-ed95-7ce7-463a991bd19b@linaro.org> Date: Fri, 8 Nov 2019 12:09:57 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org On 11/6/19 10:30 PM, Ard Biesheuvel wrote: > On Wed, 6 Nov 2019 at 15:20, Richard Henderson > wrote: >> +static inline bool has_random(void) >> +{ >> + /* >> + * We "have" RNG if either >> + * (1) every cpu in the system has RNG, or >> + * (2) in a non-preemptable context, current cpu has RNG. >> + * Case 1 is the expected case when RNG is deployed, but >> + * case 2 is present as a backup in case some big/little >> + * system only has RNG on big cpus, we can still add entropy >> + * from the interrupt handler of the big cpus. > > I don't understand the reference to the interrupt handler here. To add_interrupt_randomness(), invoked by handle_irq_event_percpu(). Better if I reword the above to include the function name? > It is > worth mentioning though that this arrangement permits > rand_initialize() to use the instructions regardless of whether they > are implemented only by the boot CPU or by all of them. Yes, I'll include that. r~