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From:   Eneas Queiroz <cotequeiroz@gmail.com>
Date:   Fri, 3 Jan 2020 11:37:45 -0300
Message-ID: <CAPxccB2w0_hmeChtSF-CUZ=dFm9srbQChhrL55fEvAH8nU-wCQ@mail.gmail.com>
Subject: Re: QCE hw-crypto DMA issues
To:     Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc:     "open list:HARDWARE RANDOM NUMBER GENERATOR CORE" 
        <linux-crypto@vger.kernel.org>
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On Fri, Jan 3, 2020 at 11:33 AM Ard Biesheuvel
<ard.biesheuvel@linaro.org> wrote:
>
> On Thu, 2 Jan 2020 at 22:09, Eneas Queiroz <cotequeiroz@gmail.com> wrote:
> >>
> >> Non-cache coherent DMA involves cache invalidation on inbound data. So
> >> if both the device and the CPU write to the same cacheline while the
> >> buffer is mapped for DMA from device to memory, one of the updates
> >> gets lost.
> >
> >
> >  Can you give me any pointers/examples of how I can make this work?
> >
>
> You could have a look at commit ed527b13d800dd515a9e6c582f0a73eca65b2e1b

Thanks, I'll check it out.