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From:   Iuliana Prodan <iuliana.prodan@nxp.com>
To:     Horia Geanta <horia.geanta@nxp.com>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Herbert Xu <herbert@gondor.apana.org.au>
CC:     "David S. Miller" <davem@davemloft.net>,
        Aymen Sghaier <aymen.sghaier@nxp.com>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        dl-linux-imx <linux-imx@nxp.com>,
        "linux-crypto@vger.kernel.org" <linux-crypto@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/2] crypto: caam - add support for i.MX8M Nano
Thread-Topic: [PATCH 1/2] crypto: caam - add support for i.MX8M Nano
Thread-Index: AQHVxMwprOIBO4cokUKxxe/ozllorA==
Date:   Tue, 7 Jan 2020 13:40:48 +0000
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References: <20200106200154.30643-1-horia.geanta@nxp.com>
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On 1/6/2020 10:02 PM, Horia Geant=E3 wrote:=0A=
> Add support for the crypto engine used in i.mx8mn (i.MX 8M "Nano"),=0A=
> which is very similar to the one used in i.mx8mq, i.mx8mm.=0A=
> =0A=
> Since the clocks are identical for all members of i.MX 8M family,=0A=
> simplify the SoC <--> clock array mapping table.=0A=
> =0A=
> Signed-off-by: Horia Geant=E3 <horia.geanta@nxp.com>=0A=
=0A=
For the series:=0A=
=0A=
Tested-by: Iuliana Prodan <iuliana.prodan@nxp.com>=0A=
Reviewed-by: Iuliana Prodan <iuliana.prodan@nxp.com>=0A=
=0A=
> ---=0A=
>   drivers/crypto/caam/ctrl.c | 8 ++++----=0A=
>   1 file changed, 4 insertions(+), 4 deletions(-)=0A=
> =0A=
> diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c=0A=
> index 6659c8d9672e..88a58a8fc533 100644=0A=
> --- a/drivers/crypto/caam/ctrl.c=0A=
> +++ b/drivers/crypto/caam/ctrl.c=0A=
> @@ -99,11 +99,12 @@ static inline int run_descriptor_deco0(struct device =
*ctrldev, u32 *desc,=0A=
>   =0A=
>   	if (ctrlpriv->virt_en =3D=3D 1 ||=0A=
>   	    /*=0A=
> -	     * Apparently on i.MX8MQ it doesn't matter if virt_en =3D=3D 1=0A=
> +	     * Apparently on i.MX8MQ, 8MM, 8MN it doesn't matter if virt_en =3D=
=3D 1=0A=
>   	     * and the following steps should be performed regardless=0A=
>   	     */=0A=
>   	    of_machine_is_compatible("fsl,imx8mq") ||=0A=
> -	    of_machine_is_compatible("fsl,imx8mm")) {=0A=
> +	    of_machine_is_compatible("fsl,imx8mm") ||=0A=
> +	    of_machine_is_compatible("fsl,imx8mn")) {=0A=
>   		clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);=0A=
>   =0A=
>   		while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&=0A=
> @@ -509,8 +510,7 @@ static const struct soc_device_attribute caam_imx_soc=
_table[] =3D {=0A=
>   	{ .soc_id =3D "i.MX6UL", .data =3D &caam_imx6ul_data },=0A=
>   	{ .soc_id =3D "i.MX6*",  .data =3D &caam_imx6_data },=0A=
>   	{ .soc_id =3D "i.MX7*",  .data =3D &caam_imx7_data },=0A=
> -	{ .soc_id =3D "i.MX8MQ", .data =3D &caam_imx7_data },=0A=
> -	{ .soc_id =3D "i.MX8MM", .data =3D &caam_imx7_data },=0A=
> +	{ .soc_id =3D "i.MX8M*", .data =3D &caam_imx7_data },=0A=
>   	{ .family =3D "Freescale i.MX" },=0A=
>   	{ /* sentinel */ }=0A=
>   };=0A=
> =0A=
=0A=