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From:   Horia Geanta <horia.geanta@nxp.com>
To:     "Andrei Botila (OSS)" <andrei.botila@oss.nxp.com>,
        Andrey Smirnov <andrew.smirnov@gmail.com>,
        "linux-crypto@vger.kernel.org" <linux-crypto@vger.kernel.org>,
        Herbert Xu <herbert@gondor.apana.org.au>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>
CC:     Chris Healy <cphealy@gmail.com>,
        Lucas Stach <l.stach@pengutronix.de>,
        Iuliana Prodan <iuliana.prodan@nxp.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        dl-linux-imx <linux-imx@nxp.com>
Subject: Re: [EXT] [PATCH v7 8/9] crypto: caam - enable prediction resistance
 in HRWNG
Thread-Topic: [EXT] [PATCH v7 8/9] crypto: caam - enable prediction resistance
 in HRWNG
Thread-Index: AQHV1TLWj2UNcbRh6Eu3gG1qYOVUqA==
Date:   Tue, 4 Feb 2020 14:19:37 +0000
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 <20200127165646.19806-9-andrew.smirnov@gmail.com>
 <882f76df-e5e4-0efc-20bc-e9bc3efd80f0@oss.nxp.com>
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On 2/4/2020 3:09 PM, Andrei Botila (OSS) wrote:=0A=
> On 1/27/2020 6:56 PM, Andrey Smirnov wrote:=0A=
>> +static bool caam_mc_skip_hwrng_init(struct caam_drv_private *ctrlpriv)=
=0A=
>> +{=0A=
>> +       return ctrlpriv->mc_en;=0A=
>> +       /*=0A=
>> +        * FIXME: Add check for MC firmware version that need=0A=
>> +        * reinitialization due to PR bit=0A=
>> +        */=0A=
>> +}=0A=
>> +=0A=
> =0A=
> Hi Andrey,=0A=
> =0A=
> Please use the following patch as a way to check for MC firmware version.=
=0A=
> This should be squashed into current PATCH v7 8/9.=0A=
> =0A=
Btw, this depends on the fsl-mc bus patch that adds fsl_mc_get_version()=0A=
bus: fsl-mc: add api to retrieve mc version=0A=
https://patchwork.kernel.org/patch/11352493/=0A=
=0A=
As already stated, I would like to take the fsl-mc bus dependency=0A=
through the crypto tree.=0A=
Greg, Herbert - are you ok with this?=0A=
=0A=
Thanks,=0A=
Horia=0A=
=0A=
> -- >8 --=0A=
> =0A=
> From: Andrei Botila <andrei.botila@nxp.com>=0A=
> Subject: [PATCH] crypto: caam - check mc firmware version before instanti=
ating=0A=
>   rng=0A=
> =0A=
> Management Complex firmware with version lower than 10.20.0=0A=
> doesn't provide prediction resistance support. Consider this=0A=
> and only instantiate rng when mc f/w version is lower.=0A=
> =0A=
> Signed-off-by: Andrei Botila <andrei.botila@nxp.com>=0A=
> ---=0A=
>   drivers/crypto/caam/Kconfig |  1 +=0A=
>   drivers/crypto/caam/ctrl.c  | 46 ++++++++++++++++++++++++++++---------=
=0A=
>   2 files changed, 36 insertions(+), 11 deletions(-)=0A=
> =0A=
> diff --git a/drivers/crypto/caam/Kconfig b/drivers/crypto/caam/Kconfig=0A=
> index fac5b2e26610..d0e833121d8c 100644=0A=
> --- a/drivers/crypto/caam/Kconfig=0A=
> +++ b/drivers/crypto/caam/Kconfig=0A=
> @@ -13,6 +13,7 @@ config CRYPTO_DEV_FSL_CAAM=0A=
>   	depends on FSL_SOC || ARCH_MXC || ARCH_LAYERSCAPE=0A=
>   	select SOC_BUS=0A=
>   	select CRYPTO_DEV_FSL_CAAM_COMMON=0A=
> +	imply FSL_MC_BUS=0A=
>   	help=0A=
>   	  Enables the driver module for Freescale's Cryptographic Accelerator=
=0A=
>   	  and Assurance Module (CAAM), also known as the SEC version 4 (SEC4).=
=0A=
> diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c=0A=
> index 167a79fa3b8a..52b98e8d5175 100644=0A=
> --- a/drivers/crypto/caam/ctrl.c=0A=
> +++ b/drivers/crypto/caam/ctrl.c=0A=
> @@ -10,6 +10,7 @@=0A=
>   #include <linux/of_address.h>=0A=
>   #include <linux/of_irq.h>=0A=
>   #include <linux/sys_soc.h>=0A=
> +#include <linux/fsl/mc.h>=0A=
>   =0A=
>   #include "compat.h"=0A=
>   #include "regs.h"=0A=
> @@ -578,14 +579,24 @@ static void caam_remove_debugfs(void *root)=0A=
>   }=0A=
>   #endif=0A=
>   =0A=
> -static bool caam_mc_skip_hwrng_init(struct caam_drv_private *ctrlpriv)=
=0A=
> +#ifdef CONFIG_FSL_MC_BUS=0A=
> +static bool check_version(struct fsl_mc_version *mc_version, u32 major,=
=0A=
> +			  u32 minor, u32 revision)=0A=
>   {=0A=
> -	return ctrlpriv->mc_en;=0A=
> -	/*=0A=
> -	 * FIXME: Add check for MC firmware version that need=0A=
> -	 * reinitialization due to PR bit=0A=
> -	 */=0A=
> +	if (mc_version->major > major)=0A=
> +		return true;=0A=
> +=0A=
> +	if (mc_version->major =3D=3D major) {=0A=
> +		if (mc_version->minor > minor)=0A=
> +			return true;=0A=
> +=0A=
> +		if (mc_version->minor =3D=3D minor && mc_version->revision > 0)=0A=
> +			return true;=0A=
> +	}=0A=
> +=0A=
> +	return false;=0A=
>   }=0A=
> +#endif=0A=
>   =0A=
>   /* Probe routine for CAAM top (controller) level */=0A=
>   static int caam_probe(struct platform_device *pdev)=0A=
> @@ -605,6 +616,7 @@ static int caam_probe(struct platform_device *pdev)=
=0A=
>   	u8 rng_vid;=0A=
>   	int pg_size;=0A=
>   	int BLOCK_OFFSET =3D 0;=0A=
> +	bool pr_support =3D false;=0A=
>   =0A=
>   	ctrlpriv =3D devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);=
=0A=
>   	if (!ctrlpriv)=0A=
> @@ -691,16 +703,28 @@ static int caam_probe(struct platform_device *pdev)=
=0A=
>   	/* Get the IRQ of the controller (for security violations only) */=0A=
>   	ctrlpriv->secvio_irq =3D irq_of_parse_and_map(nprop, 0);=0A=
>   =0A=
> +	np =3D of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc");=0A=
> +	ctrlpriv->mc_en =3D !!np;=0A=
> +	of_node_put(np);=0A=
> +=0A=
> +#ifdef CONFIG_FSL_MC_BUS=0A=
> +	if (ctrlpriv->mc_en) {=0A=
> +		struct fsl_mc_version *mc_version;=0A=
> +=0A=
> +		mc_version =3D fsl_mc_get_version();=0A=
> +		if (mc_version)=0A=
> +			pr_support =3D check_version(mc_version, 10, 20, 0);=0A=
> +		else=0A=
> +			return -EPROBE_DEFER;=0A=
> +	}=0A=
> +#endif=0A=
> +=0A=
>   	/*=0A=
>   	 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,=
=0A=
>   	 * long pointers in master configuration register.=0A=
>   	 * In case of SoCs with Management Complex, MC f/w performs=0A=
>   	 * the configuration.=0A=
>   	 */=0A=
> -	np =3D of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc");=0A=
> -	ctrlpriv->mc_en =3D !!np;=0A=
> -	of_node_put(np);=0A=
> -=0A=
>   	if (!ctrlpriv->mc_en)=0A=
>   		clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK,=0A=
>   			      MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |=0A=
> @@ -807,7 +831,7 @@ static int caam_probe(struct platform_device *pdev)=
=0A=
>   	 * already instantiated, do RNG instantiation=0A=
>   	 * In case of SoCs with Management Complex, RNG is managed by MC f/w.=
=0A=
>   	 */=0A=
> -	if (!caam_mc_skip_hwrng_init(ctrlpriv) && rng_vid >=3D 4) {=0A=
> +	if (!(ctrlpriv->mc_en && pr_support) && rng_vid >=3D 4) {=0A=
>   		ctrlpriv->rng4_sh_init =3D=0A=
>   			rd_reg32(&ctrl->r4tst[0].rdsta);=0A=
>   		/*=0A=
> =0A=