Received: by 2002:a05:6902:102b:0:0:0:0 with SMTP id x11csp134208ybt; Tue, 16 Jun 2020 19:01:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxYjUpzW9mEED5wS+AeB7EEUrhvwlFmROgzxeJvN3TgWeoUaMrRPNevfwdvCCmwfFGk3V0j X-Received: by 2002:a05:6402:c95:: with SMTP id cm21mr5043087edb.255.1592359319368; Tue, 16 Jun 2020 19:01:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1592359319; cv=none; d=google.com; s=arc-20160816; b=CmzaF76C+9tLNoYIa+Ti1h/DQW75x1jpvLnkmHThp6b6t+3D3uL7OcwFJWN+hJGLeT y69dg0wlop38gwRhZ4fJRV2o0YIoo7dyVkoP1wnvknywx98cYwTBnCy/afML/3D137fi ECMcHAYiBL9CDn4tvWSbhlwWBWvPwlV6e3hPHaTMXuUnAZ44iTCCKEBAoFcF5AKa+C+r 0erBq70R/O5wPeocEE12hmfqbjviE3DPPT1Eyg+JjqXQK19acMnjLL+ZrOLM4EhOlb2t X3jMPX35bveHGonNKcX5zpfpsGPBE6jwkrNlk1+BhKrij9zGZpkvktqComn6kDw2qRFJ aJiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:in-reply-to :mime-version:user-agent:date:message-id:references:cc:to:from :subject; bh=wPX4LIGx0A5NoeG1hIWYbPQ3TZvnwR63ls9oIaQnd+U=; b=WqI6J0+VUzvNwyaLIN/UCmzm5LsKDAk0hAjfFEATqzzJMU8fNtf2apkTSxUcypwH+u 7bsjg8ykxBc28AsVXp3m9Ei9nYF57wsEI7zbLJyKEicEzXcI/fWCRh5sheZJcMD1AioB J27mCX5xxbIDphMoAeWkMg9Crs4roA46OSp9gSlA/wRIa7ptcbFy1VmO0WfT1+XW1ikE IYpgzbs9sNrchVr74es06l1Z2pcwiu9qGrfyEQDY4OoemCcZdx3cd9JSS8K1/kD6VsvO tk8dIfCtR2cw6lcrxcsEMxvFi5mSBk2rduPEnXchBbIDvOuZ4SrqegGl9whQJkohk4+R kzeQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dm9si16072260ejc.624.2020.06.16.19.01.21; Tue, 16 Jun 2020 19:01:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726634AbgFQCBP (ORCPT + 99 others); Tue, 16 Jun 2020 22:01:15 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:6271 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726253AbgFQCBP (ORCPT ); Tue, 16 Jun 2020 22:01:15 -0400 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 01EE01E22C717AAE5C78; Wed, 17 Jun 2020 10:01:14 +0800 (CST) Received: from [127.0.0.1] (10.67.102.118) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.487.0; Wed, 17 Jun 2020 10:01:04 +0800 Subject: Re: [PATCH] crypto: hisilicon - update SEC driver module parameter From: liulongfang To: CC: , , References: <1591624871-49173-1-git-send-email-liulongfang@huawei.com> Message-ID: <2cf1904c-0c66-e962-6b07-466a6c80451f@huawei.com> Date: Wed, 17 Jun 2020 10:01:04 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <1591624871-49173-1-git-send-email-liulongfang@huawei.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.67.102.118] X-CFilter-Loop: Reflected Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org On 2020/6/8 22:01, Longfang Liu Wrote: > As stress-ng running SEC engine on the Ubuntu OS, > we found that SEC only supports two threads each with one TFM > based on the default module parameter 'ctx_q_num'. > If running more threads, stress-ng will fail since it cannot > get more TFMs. > > In order to fix this, we adjusted the default values > of the module parameters to support more TFMs. > > Signed-off-by: Longfang Liu > Signed-off-by: Zaibo Xu > --- > drivers/crypto/hisilicon/sec2/sec_main.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c > index a4cb58b..57de51f 100644 > --- a/drivers/crypto/hisilicon/sec2/sec_main.c > +++ b/drivers/crypto/hisilicon/sec2/sec_main.c > @@ -30,9 +30,9 @@ > > #define SEC_SQE_SIZE 128 > #define SEC_SQ_SIZE (SEC_SQE_SIZE * QM_Q_DEPTH) > -#define SEC_PF_DEF_Q_NUM 64 > +#define SEC_PF_DEF_Q_NUM 256 > #define SEC_PF_DEF_Q_BASE 0 > -#define SEC_CTX_Q_NUM_DEF 24 > +#define SEC_CTX_Q_NUM_DEF 2 > #define SEC_CTX_Q_NUM_MAX 32 > > #define SEC_CTRL_CNT_CLR_CE 0x301120 > @@ -191,7 +191,7 @@ static const struct kernel_param_ops sec_ctx_q_num_ops = { > }; > static u32 ctx_q_num = SEC_CTX_Q_NUM_DEF; > module_param_cb(ctx_q_num, &sec_ctx_q_num_ops, &ctx_q_num, 0444); > -MODULE_PARM_DESC(ctx_q_num, "Queue num in ctx (24 default, 2, 4, ..., 32)"); > +MODULE_PARM_DESC(ctx_q_num, "Queue num in ctx (2 default, 2, 4, ..., 32)"); > > static const struct kernel_param_ops vfs_num_ops = { > .set = vfs_num_set, Hi ALL,  I'd appreciate any comments on this patch from crypto related people. Thanks, Longfang