Received: by 2002:a05:6902:102b:0:0:0:0 with SMTP id x11csp502405ybt; Fri, 26 Jun 2020 04:54:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyeI/m+JZvYMnkd3K1olqQmnUjKkvQvx8EPylKuuRzIcuyurZt2mN3a6N7H5NQOrQ5a1vn0 X-Received: by 2002:aa7:d3cd:: with SMTP id o13mr2874140edr.176.1593172489259; Fri, 26 Jun 2020 04:54:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593172489; cv=none; d=google.com; s=arc-20160816; b=NOuw0rRw6tv12KKdjjBM55lTKIv5B9bESdRhVnMiGv2/TcCIDXwierqGS2LGPTzseO zc1phCB73mX4EahwyhGcjV3RQ7rgZzhHpv9fGkPfF3HmDe3u8LA2ZegzJKagMAaTeF6o fKxo44y6NIE3VIP4hqw0IV2yMaWULDU7jEpX/fjb6PJyqIISoL98nOgaSFJJdY/T/y0p DDgZdOQ8Ft2UU+M3zu1dt8lU21nd2R0Jx7+Eo8QybOPkwHczOZ4rKxIqykZsVslg8g9o 6H4sf8YrXS26C76Z/RqrUnIQ+8JVW+WW0QwXz7XKw7sE3L9mHBukXz9cvcKqJynbw91E PGrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=sAaoxsvRy/QrpW2y62gZzgij4MredOjw5SfX6NozU3c=; b=k6YiBNW5v3X0zADMW4wddLTCKiZrhayWCcrJovpyYgwJawK4JSNr/R62EMMTRad/wl TaHSsZhXH8kgiQlydoAo/VX9lc/dwbUybvYrXmen+woeAxVu8yrUsKG2Ls4ww61H2tDq 9bLI1+mHME1fHMrzdCr/iihMFKcvqkClRNKvq+MAyeq/ik6ketcvmhq8WI9moKbxcB7I NOke6nTc81Ij/E7wNK4QX2s/Q7ljp+de9wl5ZZmzdnEOxdA9xGfTX0+P2g++mgsuVr2u dO/cenJmmHOIWJYcgogVDMTP/RD7KEA5MvFoCPqW+vnM0GiBvMcQfAQk5lOA+dyW0zkn J0SQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id gh6si16427102ejb.689.2020.06.26.04.54.26; Fri, 26 Jun 2020 04:54:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727925AbgFZKct (ORCPT + 99 others); Fri, 26 Jun 2020 06:32:49 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:6831 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727883AbgFZKcs (ORCPT ); Fri, 26 Jun 2020 06:32:48 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 8AAF1D5B52831880FB40 for ; Fri, 26 Jun 2020 18:32:43 +0800 (CST) Received: from huawei.com (10.67.165.24) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Fri, 26 Jun 2020 18:32:39 +0800 From: Longfang Liu To: CC: Subject: [PATCH 1/5] crypto: hisilicon/sec2 - clear SEC debug regs Date: Fri, 26 Jun 2020 18:32:05 +0800 Message-ID: <1593167529-22463-2-git-send-email-liulongfang@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1593167529-22463-1-git-send-email-liulongfang@huawei.com> References: <1593167529-22463-1-git-send-email-liulongfang@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Kai Ye SEC debug registers aren't cleared even if its driver is removed, so add a clearing operation in driver removing. Signed-off-by: Kai Ye Reviewed-by: Longfang Liu --- drivers/crypto/hisilicon/sec2/sec_main.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c index a4cb58b..c2567cc 100644 --- a/drivers/crypto/hisilicon/sec2/sec_main.c +++ b/drivers/crypto/hisilicon/sec2/sec_main.c @@ -346,10 +346,17 @@ static int sec_set_user_domain_and_cache(struct hisi_qm *qm) /* sec_debug_regs_clear() - clear the sec debug regs */ static void sec_debug_regs_clear(struct hisi_qm *qm) { + int i; + /* clear current_qm */ writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF); writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF); + /* clear sec dfx regs */ + writel(0x1, qm->io_base + SEC_CTRL_CNT_CLR_CE); + for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++) + readl(qm->io_base + sec_dfx_regs[i].offset); + /* clear rdclr_en */ writel(0x0, qm->io_base + SEC_CTRL_CNT_CLR_CE); -- 2.8.1