Received: by 2002:a05:6902:102b:0:0:0:0 with SMTP id x11csp615571ybt; Mon, 6 Jul 2020 18:16:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwtmeosc5j6ICYoUHGfrQuSljIA3yoxcltEM8VdrMwMK9WE9vQDY38z3XhZTdbxO9DW3oF3 X-Received: by 2002:a50:9e2e:: with SMTP id z43mr60153669ede.385.1594084619438; Mon, 06 Jul 2020 18:16:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594084619; cv=none; d=google.com; s=arc-20160816; b=LH6u+4yDw9mGRdUpTr8Uag/3yNTgqY/yDEhHlBC6dKjoQJRdkvVW2Z8tA4Gc7YCCbk mNGusuGYySQVDPeG7tseR5fLyNr7Yigal7cKquQHOYUGcm0tcdlKohdKyoA6JiKQqwE9 71VI+TMddmHh41Q90PFGP97lI/xUrjiJUcBpr7JaqYotwJ0okZrIYuLExF0sQU3VsyiX GLdM7M0I38CBs982KjrinISbenP0xQPUU8lvNCg0XAmdsap4fKakOGNT37l+OZTuiJrv aH91iDmfd/j/xqb1m+VZCw50qVCL1YA/WRAfbcmejvOGDjwQrYMdM0QANdtLztrJh2WS 31GA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=WsyYBO/QS1YVTN4AM30/zEtYCMdxLX8Umo7xnxg8BBE=; b=hyQs8LVirBdt6wNgxJ5Npj7zBGy3SVL3LVJ51WYLZVBNOGRm0XlrKKwINAWiN8ZpFY iwvNMfqjTinkcO5OH8Q96gZzdkhz7dFmyVXdwSzliu7r6/mvl9gdc1iFAIcjlGW96Kt/ dM52En00Hj2qTJ9VRleQRIuoe9BG/Bg4l9KBp9y2DdEFCHayNYV/uFHh4smH0eViThDD nfVeax5HE/hSTW6fAgPI7GSbzXHNp4XwWvrnsH0HKK1yCCNRV9ti5JYKdHzs8P9fDtM7 RBUX53+GXb2QC0kLCoSubTfkKDmmFKI1vKCd2RBJ8Yb9trt8pu8HV8PaptoRebytzmUW U+Xw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id t19si13075509eju.562.2020.07.06.18.16.23; Mon, 06 Jul 2020 18:16:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727038AbgGGBQU (ORCPT + 99 others); Mon, 6 Jul 2020 21:16:20 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:7258 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726961AbgGGBQU (ORCPT ); Mon, 6 Jul 2020 21:16:20 -0400 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 96AA440B646FA4722004 for ; Tue, 7 Jul 2020 09:16:16 +0800 (CST) Received: from huawei.com (10.67.165.24) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.487.0; Tue, 7 Jul 2020 09:16:15 +0800 From: Longfang Liu To: CC: Subject: [PATCH v2 1/5] crypto: hisilicon/sec2 - clear SEC debug regs Date: Tue, 7 Jul 2020 09:15:37 +0800 Message-ID: <1594084541-22177-2-git-send-email-liulongfang@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1594084541-22177-1-git-send-email-liulongfang@huawei.com> References: <1594084541-22177-1-git-send-email-liulongfang@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Kai Ye SEC debug registers aren't cleared even if its driver is removed, so add a clearing operation in driver removing. Signed-off-by: Kai Ye Reviewed-by: Longfang Liu --- drivers/crypto/hisilicon/sec2/sec_main.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c index 57de51f..d5f0589 100644 --- a/drivers/crypto/hisilicon/sec2/sec_main.c +++ b/drivers/crypto/hisilicon/sec2/sec_main.c @@ -346,10 +346,17 @@ static int sec_set_user_domain_and_cache(struct hisi_qm *qm) /* sec_debug_regs_clear() - clear the sec debug regs */ static void sec_debug_regs_clear(struct hisi_qm *qm) { + int i; + /* clear current_qm */ writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF); writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF); + /* clear sec dfx regs */ + writel(0x1, qm->io_base + SEC_CTRL_CNT_CLR_CE); + for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++) + readl(qm->io_base + sec_dfx_regs[i].offset); + /* clear rdclr_en */ writel(0x0, qm->io_base + SEC_CTRL_CNT_CLR_CE); -- 2.8.1