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Date:   Thu, 16 Jul 2020 11:21:36 +0200
From:   Sven Auhagen <sven.auhagen@voleatech.de>
To:     "Van Leeuwen, Pascal" <pvanleeuwen@rambus.com>
Cc:     Herbert Xu <herbert@gondor.apana.org.au>,
        "linux-crypto@vger.kernel.org" <linux-crypto@vger.kernel.org>
Subject: Re: [PATCH 1/1] inside-secure irq balance
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On Thu, Jul 16, 2020 at 08:44:23AM +0000, Van Leeuwen, Pascal wrote:
> > -----Original Message-----
> > From: linux-crypto-owner@vger.kernel.org <linux-crypto-owner@vger.kernel.org> On Behalf Of Herbert Xu
> > Sent: Thursday, July 16, 2020 9:22 AM
> > To: Sven Auhagen <sven.auhagen@voleatech.de>
> > Cc: linux-crypto@vger.kernel.org
> > Subject: Re: [PATCH 1/1] inside-secure irq balance
> >
> > <<< External Email >>>
> > Sven Auhagen <sven.auhagen@voleatech.de> wrote:
> > >
> > > +       // Set affinity
> > > +       cpu = ring_id % num_online_cpus();
> > > +       irq_set_affinity_hint(irq, get_cpu_mask(cpu));
> > > +
> >
> > This doesn't look right.  There is no guarantee that the online
> > CPUs are the lowest bits in the bitmask.  Also, what are you going
> > to do when the CPUs go down (or up)?
> >

You are correct, let me have a look at how to get the cpu bit correctly.
Well everything runs on the first CPU now, what do you do if that does down or up?
I think there is no mechanism in general at the moment for the current or my implementation.

> 
> Ok, I was just about to test this patch with my hardware, but I suppose I can spare myself the
> trouble if it doesn't make sense. I already had a hunch it was too simplistic for general use.
> However, he does get a very significant speed boost out of this, which makes sense as having
> the interrupts properly distributed AND pinned to a fixed CPU ensures proper workload
> distribution and cache locality. In fact, this was the whole idea behind having multiple rings
> and interrupts.
> 
> So is there a better way to achieve the same goal from the driver? Or is this really something
> you cannot fix in the crypto driver itself?
> 
> > Cheers,
> > --
> > Email: Herbert Xu <herbert@gondor.apana.org.au>
> > Home Page: https://eur03.safelinks.protection.outlook.com/?url=http:%2F%2Fgondor.apana.org.au%2F~herbert%2F&amp;data=02%7C01%7Csven.auhagen%40voleatech.de%7C42783499b8fa4d11a9c608d8296474d2%7Cb82a99f679814a7295344d35298f847b%7C0%7C0%7C637304858734739951&amp;sdata=GNleSUVRQe56P%2BkG6OQ3JH7AkXzKve6UP6ai5dKpN0M%3D&amp;reserved=0
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> 
> Regards,
> Pascal van Leeuwen
> Silicon IP Architect Multi-Protocol Engines, Rambus Security
> Rambus ROTW Holding BV
> +31-73 6581953
> 
> Note: The Inside Secure/Verimatrix Silicon IP team was recently acquired by Rambus.
> Please be so kind to update your e-mail address book with my new e-mail address.
> 
> 
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