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From:   Srujana Challa <schalla@marvell.com>
To:     Herbert Xu <herbert@gondor.apana.org.au>
CC:     "davem@davemloft.net" <davem@davemloft.net>,
        "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
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        Suheil Chandran <schandran@marvell.com>,
        Narayana Prasad Raju Athreya <pathreya@marvell.com>,
        Sunil Kovvuri Goutham <sgoutham@marvell.com>,
        Linu Cherian <lcherian@marvell.com>,
        "Geethasowjanya Akula" <gakula@marvell.com>,
        Jerin Jacob Kollanukkaran <jerinj@marvell.com>
Subject: RE: [PATCH v2 2/3] drivers: crypto: add support for OCTEONTX2 CPT
 engine
Thread-Topic: [PATCH v2 2/3] drivers: crypto: add support for OCTEONTX2 CPT
 engine
Thread-Index: AQHWbMTfW+P0JoWQZkyWfmrU0nLSuak1PvSAgCNkG6A=
Date:   Fri, 4 Sep 2020 13:45:38 +0000
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> Subject: Re: [PATCH v2 2/3] drivers: crypto: add support for OCTEONTX2 CP=
T
> engine
>=20
> On Fri, Aug 07, 2020 at 07:39:19PM +0530, Srujana Challa wrote:
> >
> > +#if defined(CONFIG_ARM64)
> > +static inline long otx2_lmt_flush(void *ioreg)
> > +{
> > +	long result =3D 0;
> > +
> > +	__asm__ volatile(".cpu  generic+lse\n"
> > +			 "ldeor xzr, %0, [%1]\n"
> > +			 : "=3Dr" (result)
> > +			 : "r" (ioreg) : "memory");
> > +
> > +	return result;
> > +}
> > +
> > +#else
> > +#define otx2_lmt_flush(addr)     ({ 0; })
> > +#endif
>=20
> This is not acceptable.  Please work out a way with the ARM folks
> to fix this without adding assembly code in a driver.
>=20
This block of code is used for LMT store operations. The LMT store operatio=
n
is specific to our platform, and this uses the "ldeor" instruction(which is
actually an LSE atomic instruction available on v8.1 CPUs) targeting the
IO address.
We add it in the driver since we want LMT store to work even if LSE_ATOMICS
is disabled.

Thanks,
Srujana

> Thanks,
> --
> Email: Herbert Xu <herbert@gondor.apana.org.au>
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