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[23.128.96.18]) by mx.google.com with ESMTP id p10si1976887edq.458.2020.10.06.02.50.50; Tue, 06 Oct 2020 02:51:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=NEMirvyv; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725960AbgJFJut (ORCPT + 99 others); Tue, 6 Oct 2020 05:50:49 -0400 Received: from mail.kernel.org ([198.145.29.99]:49168 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725939AbgJFJut (ORCPT ); Tue, 6 Oct 2020 05:50:49 -0400 Received: from mail-oi1-f174.google.com (mail-oi1-f174.google.com [209.85.167.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 914852080A; Tue, 6 Oct 2020 09:50:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1601977848; bh=PeSuqk/VTDEBoJqvvMEQqoW1Xu2MaaV6ZO1NmFYY/kw=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=NEMirvyv6rsJ5s455o1dpjT1Vjx+M2kXvbXTeVrHWhjFRAvhXB3uxg9F+40YqOQlJ xXBNGuieCh82T2WSNKT7Svuu4U6KyQCI/rzPdd10RdyCQcgxm4I7y85L/wEdpKJVo+ qI+jJeETZMN1hsbWgzRvxLVTADUqzqbCqPr5bg8g= Received: by mail-oi1-f174.google.com with SMTP id m128so11976720oig.7; Tue, 06 Oct 2020 02:50:48 -0700 (PDT) X-Gm-Message-State: AOAM531GzzmZm7MS3tKzsrB+qc6fiOekSkOhF42RcOOaTmaFBbRnuuKn Yjgdfv0QqfD7hi2x44E5VESiuAocDWsrwXnyPc0= X-Received: by 2002:a05:6808:8e5:: with SMTP id d5mr2231046oic.33.1601977847799; Tue, 06 Oct 2020 02:50:47 -0700 (PDT) MIME-Version: 1.0 References: <20201005181804.1331237-1-jeremy.linton@arm.com> <20201006093817.GV6642@arm.com> In-Reply-To: <20201006093817.GV6642@arm.com> From: Ard Biesheuvel Date: Tue, 6 Oct 2020 11:50:36 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [BUG][PATCH] arm64: bti: fix BTI to handle local indirect branches To: Dave Martin Cc: Jeremy Linton , Herbert Xu , Catalin Marinas , Linux Kernel Mailing List , Mark Brown , Linux Crypto Mailing List , Will Deacon , "David S. Miller" , Linux ARM Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org On Tue, 6 Oct 2020 at 11:38, Dave Martin wrote: > > On Mon, Oct 05, 2020 at 02:24:47PM -0500, Jeremy Linton wrote: > > Hi, > > > > On 10/5/20 1:54 PM, Ard Biesheuvel wrote: > > >On Mon, 5 Oct 2020 at 20:18, Jeremy Linton wrote: > > >> > > >>The AES code uses a 'br x7' as part of a function called by > > >>a macro, that ends up needing a BTI_J as a target. > > > > > >Could we instead just drop the tail call, i.e, replace it with a ret > > >and do a 'bl' after it returns? The indirect call does not really > > >serve a purpose here anyway > > > > Yes, that is an option, it adds an extra ret. Which probably doesn't mean > > much in most cases. I assumed this code was optimized this way because it > > mattered somewhere. > > Since this really does seem to be a tail-call and since x16 and x17 > appear to be otherwise unused here, can we not just use x16 or x17 > instead of x7? > > This relies on there being no other calls to veneered functions in the > mix, but this code is all in a single section so that shouldn't be a > concern. > > Due to the magic status of x16 and x17 in br instructions, the resulting > jump should be compatible with BTI c. I think this matches how the > compiler should typically compile tail-calls. > Ah, excellent point. That is definitely the cleanest fix.