Received: by 2002:a05:6a10:6744:0:0:0:0 with SMTP id w4csp4621144pxu; Tue, 13 Oct 2020 03:05:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJymgn8Yri0HgwUnvIHthnv64NNuzu4gJ/Avm1HZwu3X101tDbQqkoqkMymtCYxWLc8Q5TQb X-Received: by 2002:a17:906:2bc5:: with SMTP id n5mr31965564ejg.476.1602583527726; Tue, 13 Oct 2020 03:05:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1602583527; cv=none; d=google.com; s=arc-20160816; b=K6MtuUuLEfV3PD8ae7tP629su86dZyh414ejpD1+/RjdspeIGbrgOKOTgFlZjWoWy6 MMvNocpbQCFz+DsdORkafEjBBNQxqCFZGLNOqodFQMIKZv60NW+CEQvYaRdGw3Fs+eZ6 36m7CoBrsMW/xmF7efDf2YWAsIDRKJgUf70UPJ0YMM7VoyOuVybfyEC1u76527DfCpQM cCg+V3bCszeoA4nWhWE3j8Ea2kwsK8QnFugLHAFvxMAtyFYuf2EwH7PiL+Xe4CyEKkdk jF2CAERiAWeoJGsR3NFuVmdI/cBnbI2fOOM4KXj8dJJPB6htZRYa+8Hr1W9xMSqFlnGp xPVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :ironport-sdr:ironport-sdr; bh=obgUvGdpKaZNTSXVRKNFD1fKDwNIoadPPdm6IRfNPhM=; b=WivKE4mk4I/enG02v/r/MRiNATtDDmlDMn37L2MLIUpsLFx8YZzd4nIAI3bsxH7Api fAxJx6uGVuLhlDLstDfdsicXTkFQdPKvtZRct4+B2kIkF3X83utsWYLSMbAI+6Uzxg58 suqawkMLnT9cu1+PEypWxF5dbxlMge8jFnsmHD5GMUhCmruqzWQYAK93gKRSRnPp/hY1 5VojjUrqTNSTpOR4nbw1TCIj4lnQBKmIHdSX1KPj+uW26sqNa114AqzrqqNUXyqzy9C5 0sra0KS6dS9mJ7UK9YnIDDBZ3eESFLOgQY9SSsp/4v0BanohE4S6JE4GTZRcX0yW4F9n iwVw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id s24si15317722edi.129.2020.10.13.03.05.04; Tue, 13 Oct 2020 03:05:27 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387764AbgJLUjs (ORCPT + 99 others); Mon, 12 Oct 2020 16:39:48 -0400 Received: from mga09.intel.com ([134.134.136.24]:34081 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387830AbgJLUjq (ORCPT ); Mon, 12 Oct 2020 16:39:46 -0400 IronPort-SDR: GCuXdty2PwHmOECC5byjjSnaSW6tI+QCfCcO/CTrTPa7dGRntBtkvnzNN9py7t7RvQrCHmEpWT PU5Jz+/P5zOQ== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="165913172" X-IronPort-AV: E=Sophos;i="5.77,367,1596524400"; d="scan'208";a="165913172" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Oct 2020 13:39:45 -0700 IronPort-SDR: Owa7jcMrtMb6d5ed6JugewsNtLX+IfSHFPH6SURJIDr3JrJsiAxNNxn4rnaZ7b3PUJKHhASBTX Pz6DdWDdq6HQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,367,1596524400"; d="scan'208";a="299328249" Received: from silpixa00400314.ir.intel.com (HELO silpixa00400314.ger.corp.intel.com) ([10.237.222.51]) by fmsmga007.fm.intel.com with ESMTP; 12 Oct 2020 13:39:43 -0700 From: Giovanni Cabiddu To: herbert@gondor.apana.org.au Cc: linux-crypto@vger.kernel.org, qat-linux@intel.com, Giovanni Cabiddu , Wojciech Ziemba , Fiona Trahe , Andy Shevchenko Subject: [PATCH 23/31] crypto: qat - remove hardcoded bank irq clear flag mask Date: Mon, 12 Oct 2020 21:38:39 +0100 Message-Id: <20201012203847.340030-24-giovanni.cabiddu@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201012203847.340030-1-giovanni.cabiddu@intel.com> References: <20201012203847.340030-1-giovanni.cabiddu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Replace hardcoded value of the bank interrupt clear flag mask with a value calculated on the fly which is based on the number of rings present in a bank. This is to support devices that have a number of rings per bank different than 16. Signed-off-by: Giovanni Cabiddu Reviewed-by: Wojciech Ziemba Reviewed-by: Fiona Trahe Reviewed-by: Andy Shevchenko --- drivers/crypto/qat/qat_common/adf_transport.c | 4 ++-- drivers/crypto/qat/qat_common/adf_transport_access_macros.h | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/crypto/qat/qat_common/adf_transport.c b/drivers/crypto/qat/qat_common/adf_transport.c index dd8f94fcb9a8..5a7030acdc33 100644 --- a/drivers/crypto/qat/qat_common/adf_transport.c +++ b/drivers/crypto/qat/qat_common/adf_transport.c @@ -374,6 +374,7 @@ static int adf_init_bank(struct adf_accel_dev *accel_dev, struct adf_hw_device_data *hw_data = accel_dev->hw_device; u8 num_rings_per_bank = hw_data->num_rings_per_bank; struct adf_hw_csr_ops *csr_ops = &hw_data->csr_ops; + u32 irq_mask = BIT(num_rings_per_bank) - 1; struct adf_etr_ring_data *ring; struct adf_etr_ring_data *tx_ring; u32 i, coalesc_enabled = 0; @@ -431,8 +432,7 @@ static int adf_init_bank(struct adf_accel_dev *accel_dev, goto err; } - csr_ops->write_csr_int_flag(csr_addr, bank_num, - ADF_BANK_INT_FLAG_CLEAR_MASK); + csr_ops->write_csr_int_flag(csr_addr, bank_num, irq_mask); csr_ops->write_csr_int_srcsel(csr_addr, bank_num); return 0; diff --git a/drivers/crypto/qat/qat_common/adf_transport_access_macros.h b/drivers/crypto/qat/qat_common/adf_transport_access_macros.h index 12b1605a740e..3b6b0267bbec 100644 --- a/drivers/crypto/qat/qat_common/adf_transport_access_macros.h +++ b/drivers/crypto/qat/qat_common/adf_transport_access_macros.h @@ -4,7 +4,6 @@ #define ADF_TRANSPORT_ACCESS_MACROS_H #include "adf_accel_devices.h" -#define ADF_BANK_INT_FLAG_CLEAR_MASK 0xFFFF #define ADF_RING_CONFIG_NEAR_FULL_WM 0x0A #define ADF_RING_CONFIG_NEAR_EMPTY_WM 0x05 #define ADF_COALESCING_MIN_TIME 0x1FF -- 2.26.2