Received: by 2002:a05:6a10:f347:0:0:0:0 with SMTP id d7csp1160548pxu; Fri, 27 Nov 2020 00:50:25 -0800 (PST) X-Google-Smtp-Source: ABdhPJzWhpYaHmznDwqseFCImczuv0hYyj7DCstygqDXc5StWKI7ciFyDTBhHqgrE29tvh69drDQ X-Received: by 2002:a50:a40a:: with SMTP id u10mr6396031edb.16.1606467025404; Fri, 27 Nov 2020 00:50:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606467025; cv=none; d=google.com; s=arc-20160816; b=K8hSFHyV7yBmlFyAClays1cfnjqufmWR9Cvv1iEwCW3NmYl9CMU2wHiYjsTC69nmCz eldJSJgRWE14HsHoiZdkIBLxxy/k8NLeDfPWSwigwWwknmSRYqzOZeL40OTzpbhjNzuT +HI7Ijkbd5gPJJk9V7CsBJV1oY+o2VcdpCguvuHZUSJNVvYWYDH1UGHgrM006ZXEGEd1 clhVe3X2eqpjczmcrEKBdRR2/SufZC9pS7FvNFA3ZvPK0LLX+LoK0a0Nvjxl1PjNWvAZ 3t0bPySV6knKC3XyQysUhh9qMdBVeNJB46dl8JgmRwyvLWD+ZzzlAE/EANBKkWeqxJb9 fQtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:user-agent:in-reply-to:content-disposition :mime-version:references:message-id:subject:cc:to:from:date; bh=vvQThNZ4z9rjLbt2RNOBruNct5bkZtj61hX4/g33uRw=; b=SKkij4OqPpns0nHnzPEN2jq9ZqYeb6ETF9jLXvk1+s0B8RQsqttIj6X/QvqQXVzHpG EQyBWSnsSqdJmlNivR5BrG33HLbAY8E0P+q4HWaWZMOyOlV6ldSHCydjv/OSIY9tDJgC PZ2taDJ0gVBvVoYtr8LncoJi0jvU81328SepL32sqBmgi6u2WILJ29djZvpTAQMxqRKg X+bUIKCJ1AaX5Dx/cEro86HWEkDgtFhoonghKsN3qR7wVj0oCYOzS3y5tgF/nWDMIDse KNCW16YF+JMf9Uowzhgd8rxURgYHVUUcf7M9R6uqVFIAwhOZ59tIPk61VPpFN1imNEBJ btzw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id hb18si13556ejb.10.2020.11.27.00.50.02; Fri, 27 Nov 2020 00:50:25 -0800 (PST) Received-SPF: pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2392574AbgK0GZW (ORCPT + 99 others); Fri, 27 Nov 2020 01:25:22 -0500 Received: from helcar.hmeau.com ([216.24.177.18]:33422 "EHLO fornost.hmeau.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728043AbgK0GZW (ORCPT ); Fri, 27 Nov 2020 01:25:22 -0500 Received: from gwarestrin.arnor.me.apana.org.au ([192.168.0.7]) by fornost.hmeau.com with smtp (Exim 4.92 #5 (Debian)) id 1kiXBx-0000x6-0Y; Fri, 27 Nov 2020 17:25:14 +1100 Received: by gwarestrin.arnor.me.apana.org.au (sSMTP sendmail emulation); Fri, 27 Nov 2020 17:25:12 +1100 Date: Fri, 27 Nov 2020 17:25:12 +1100 From: Herbert Xu To: Thara Gopinath Cc: agross@kernel.org, bjorn.andersson@linaro.org, davem@davemloft.net, robh+dt@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [Patch v2 0/6] Enable Qualcomm Crypto Engine on sdm845 Message-ID: <20201127062512.GB11448@gondor.apana.org.au> References: <20201119155233.3974286-1-thara.gopinath@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201119155233.3974286-1-thara.gopinath@linaro.org> User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org On Thu, Nov 19, 2020 at 10:52:27AM -0500, Thara Gopinath wrote: > Qualcomm crypto engine supports hardware accelerated algorithms for > encryption and authentication. Enable support for aes,des,3des encryption > algorithms and sha1,sha256, hmac(sha1),hmac(sha256) authentication > algorithms on sdm845.The patch series has been tested using the kernel > crypto testing module tcrypto.ko. > > v1->v2: > - Rebased to linux-next v5.10-rc4. > - Fixed subject line format in all patches as per Bjorn's feedback. > > Thara Gopinath (6): > dt-binding:clock: Add entry for crypto engine RPMH clock resource > clk:qcom:rpmh: Add CE clock on sdm845. > drivers:crypto:qce: Enable support for crypto engine on sdm845. > drivers:crypto:qce: Fix SHA result buffer corruption issues. > dts:qcom:sdm845: Add dt entries to support crypto engine. > devicetree:bindings:crypto: Extend qcom-qce binding to add support for > crypto engine version 5.4 > > .../devicetree/bindings/crypto/qcom-qce.txt | 4 ++- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 30 +++++++++++++++++++ > drivers/clk/qcom/clk-rpmh.c | 2 ++ > drivers/crypto/qce/core.c | 17 ++++++++++- > drivers/crypto/qce/sha.c | 2 +- > include/dt-bindings/clock/qcom,rpmh.h | 1 + > 6 files changed, 53 insertions(+), 3 deletions(-) Patches 3-4 applied. Thanks. -- Email: Herbert Xu Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt