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[23.128.96.18]) by mx.google.com with ESMTP id u15si8853600edv.291.2020.12.13.06.58.57; Sun, 13 Dec 2020 06:59:27 -0800 (PST) Received-SPF: pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b="R/u+XyxM"; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2438818AbgLLKy7 (ORCPT + 99 others); Sat, 12 Dec 2020 05:54:59 -0500 Received: from mail.kernel.org ([198.145.29.99]:56384 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726591AbgLLKy7 (ORCPT ); Sat, 12 Dec 2020 05:54:59 -0500 X-Gm-Message-State: AOAM530MgMyFxV64AKMHo3/fqrGgkMYA46ZH1Q7F0pR3uRNBZzNKIgli pbahEjyBu04PfwTzrdC2uMNiaHKTDGyXmOLIIm8= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1607770458; bh=I2k6JcKef6p2Y07EpasqSQz/C60x4ofi+mzysUW+G74=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=R/u+XyxMYztIqz8elA/Sbr1Ln9z4A8v83dLt3pCpLOD/ZbY1zpSX1Yomgz6SflZrU LMvGh6LS3Tja5Li8eCYqSENBJc6/0usA0wIhkEK/I8prf+6p3i/mOxV92bpCsdz5av utUoGJrT8BdlMWKJFR830qULVrpSuy4XleiRLctvklEk+nD6b0riDEyo+E4teI3Mcf 8un+dmK7m+f4tTG0tQtLHpDokw01aO2T9OUeSTlR1IlkhKUBk5swqAO5yG4K7S7txC CcI75E11StEX6xBMTUp+8huAH6NLFuJ9Ti87z0aY0cj2zqkXsl0uVdzm0CXqAaOqH+ LH92h+vWMxm/Q== X-Received: by 2002:a05:6830:1c24:: with SMTP id f4mr12718462ote.108.1607770458126; Sat, 12 Dec 2020 02:54:18 -0800 (PST) MIME-Version: 1.0 References: <1607686144-2604-1-git-send-email-TonyWWang-oc@zhaoxin.com> In-Reply-To: From: Ard Biesheuvel Date: Sat, 12 Dec 2020 11:54:07 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] crypto: x86/crc32c-intel - Don't match some Zhaoxin CPUs To: Eric Biggers Cc: Tony W Wang-oc , Herbert Xu , "David S. Miller" , Thomas Gleixner , Ingo Molnar , Borislav Petkov , X86 ML , "H. Peter Anvin" , Linux Crypto Mailing List , Linux Kernel Mailing List , TimGuo-oc@zhaoxin.com, CooperYan@zhaoxin.com, QiyuanWang@zhaoxin.com, HerryYang@zhaoxin.com, CobeChen@zhaoxin.com, SilviaZhao@zhaoxin.com Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org On Sat, 12 Dec 2020 at 10:36, Ard Biesheuvel wrote: > > On Fri, 11 Dec 2020 at 20:07, Eric Biggers wrote: > > > > On Fri, Dec 11, 2020 at 07:29:04PM +0800, Tony W Wang-oc wrote: > > > The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2. > > > On platforms with Zhaoxin CPUs supporting this X86 feature, When > > > crc32c-intel and crc32c-generic are both registered, system will > > > use crc32c-intel because its .cra_priority is greater than > > > crc32c-generic. This case expect to use crc32c-generic driver for > > > some Zhaoxin CPUs to get performance gain, So remove these Zhaoxin > > > CPUs support from crc32c-intel. > > > > > > Signed-off-by: Tony W Wang-oc > > > > Does this mean that the performance of the crc32c instruction on those CPUs is > > actually slower than a regular C implementation? That's very weird. > > > > This driver does not use CRC instructions, but carryless > multiplication and aggregation. So I suppose the pclmulqdq instruction > triggers some pathological performance limitation here. > Just noticed it uses both crc instructions and pclmulqdq instructions. Sorry for the noise. > That means the crct10dif driver probably needs the same treatment. Tony, can you confirm that the problem is in the CRC instructions and not in the PCLMULQDQ code path that supersedes it when available?