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[23.128.96.18]) by mx.google.com with ESMTP id 61si2571048edk.598.2020.12.14.01.38.55; Mon, 14 Dec 2020 01:39:19 -0800 (PST) Received-SPF: pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2438004AbgLNCaC (ORCPT + 99 others); Sun, 13 Dec 2020 21:30:02 -0500 Received: from ZXSHCAS1.zhaoxin.com ([203.148.12.81]:27106 "EHLO ZXSHCAS1.zhaoxin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730312AbgLNC3z (ORCPT ); Sun, 13 Dec 2020 21:29:55 -0500 Received: from zxbjmbx1.zhaoxin.com (10.29.252.163) by ZXSHCAS1.zhaoxin.com (10.28.252.161) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Mon, 14 Dec 2020 10:29:04 +0800 Received: from [10.32.56.37] (10.32.56.37) by zxbjmbx1.zhaoxin.com (10.29.252.163) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Mon, 14 Dec 2020 10:29:02 +0800 Subject: Re: [PATCH] crypto: x86/crc32c-intel - Don't match some Zhaoxin CPUs To: Ard Biesheuvel , Eric Biggers CC: Herbert Xu , "David S. Miller" , Thomas Gleixner , Ingo Molnar , Borislav Petkov , X86 ML , "H. Peter Anvin" , Linux Crypto Mailing List , Linux Kernel Mailing List , , , , , , References: <1607686144-2604-1-git-send-email-TonyWWang-oc@zhaoxin.com> From: Tony W Wang-oc Message-ID: <7b826cf5-7371-77a2-b4c1-a6533787031e@zhaoxin.com> Date: Mon, 14 Dec 2020 10:29:01 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.32.56.37] X-ClientProxiedBy: ZXSHCAS1.zhaoxin.com (10.28.252.161) To zxbjmbx1.zhaoxin.com (10.29.252.163) Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org On 12/12/2020 18:54, Ard Biesheuvel wrote: > On Sat, 12 Dec 2020 at 10:36, Ard Biesheuvel wrote: >> >> On Fri, 11 Dec 2020 at 20:07, Eric Biggers wrote: >>> >>> On Fri, Dec 11, 2020 at 07:29:04PM +0800, Tony W Wang-oc wrote: >>>> The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2. >>>> On platforms with Zhaoxin CPUs supporting this X86 feature, When >>>> crc32c-intel and crc32c-generic are both registered, system will >>>> use crc32c-intel because its .cra_priority is greater than >>>> crc32c-generic. This case expect to use crc32c-generic driver for >>>> some Zhaoxin CPUs to get performance gain, So remove these Zhaoxin >>>> CPUs support from crc32c-intel. >>>> >>>> Signed-off-by: Tony W Wang-oc >>> >>> Does this mean that the performance of the crc32c instruction on those CPUs is >>> actually slower than a regular C implementation? That's very weird. >>> >> >> This driver does not use CRC instructions, but carryless >> multiplication and aggregation. So I suppose the pclmulqdq instruction >> triggers some pathological performance limitation here. >> > > Just noticed it uses both crc instructions and pclmulqdq instructions. > Sorry for the noise. > >> That means the crct10dif driver probably needs the same treatment. > > Tony, can you confirm that the problem is in the CRC instructions and > not in the PCLMULQDQ code path that supersedes it when available? CRC instructions. sincerely Tony