Received: by 2002:a05:6a10:f347:0:0:0:0 with SMTP id d7csp85156pxu; Wed, 6 Jan 2021 22:20:21 -0800 (PST) X-Google-Smtp-Source: ABdhPJz8vRwUkJw0ImREwiVd9DpXeHTB6io9js+Q7W6newwZJ9oABPqDgSiJkLo550TnLen8jb9O X-Received: by 2002:a50:f307:: with SMTP id p7mr502869edm.368.1610000420952; Wed, 06 Jan 2021 22:20:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610000420; cv=none; d=google.com; s=arc-20160816; b=DRH9sEqxzxEhS58FE9EzEw0Wukm5mIhkXPTmPBYQC7Fyco4unnEwCuYeYyvT8jAVvS TEHWxarEvAJvofithVw3a97QDbyG91cphD172c/ZvggQ9vVYl+A1LHOqdd8AX4otWB8/ ea+FTJLoUAMVsr8r/QYk99sOmM4jU8vRAo+6BbRW3lGFwXnY5xHRBw/KGrdjbhTiKEed I8Pa9AEpzTnEDnr79yu59YSmZ1T69RLuIHUnEGDEZcswKFFfHfpku4FkJCLlJo3qLZaJ 9HqD7ak/5p12hlVYJ4+fdX1xz/0SRcC4aN+HgTSpgnCQIhF8m0haNS3OAB5UMX5cPYHs 66HA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:message-id:date:subject:cc:to:from; bh=xQTVk3seNYJ6SXSZ5IShzo0lQaSU+QeZYkDGJ2RGVKs=; b=CrbUTS9/nzhh17Nz5uLYuPSabvdw2D6/LtGIFXOaTdGPqUVpnY+sFZwVxXYgsC5hxw /3vJUqoLyIBqiytjFOPKQXwshJ/4C/S0VtIvViOoAmUhAtlP5TBV2m9tVEi7MA2+OciT FE44/Sk9CJc4R4JSdKasE2ZC3ESMuEEVz1skm9EnSzv6dFEiMXkO4gA2GAEoP6us9VzX svUgexL10AUsCn+8OBcZ9GWcmC8CQ9VtTwwCvEHHPwJqO8tWXNkUjTaKm3TETWRIeNIX s2u/zxAxOpoo25H0LBwch0YFZTBBaaKhYbD7Vz2Cb6yZ8u7PPI0n/+WUIBDLNwg6y1ah DwZg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id n22si1780585ejr.464.2021.01.06.22.20.00; Wed, 06 Jan 2021 22:20:20 -0800 (PST) Received-SPF: pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725763AbhAGGT7 (ORCPT + 99 others); Thu, 7 Jan 2021 01:19:59 -0500 Received: from ZXSHCAS1.zhaoxin.com ([203.148.12.81]:52807 "EHLO ZXSHCAS1.zhaoxin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725306AbhAGGT7 (ORCPT ); Thu, 7 Jan 2021 01:19:59 -0500 Received: from zxbjmbx1.zhaoxin.com (10.29.252.163) by ZXSHCAS1.zhaoxin.com (10.28.252.161) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 7 Jan 2021 14:19:15 +0800 Received: from tony-HX002EA.zhaoxin.com (10.32.56.37) by zxbjmbx1.zhaoxin.com (10.29.252.163) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Thu, 7 Jan 2021 14:19:12 +0800 From: Tony W Wang-oc To: , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v1 0/3] crypto: x86/crc32c-intel - Exclude some Zhaoxin CPUs Date: Thu, 7 Jan 2021 14:19:05 +0800 Message-ID: <1610000348-17316-1-git-send-email-TonyWWang-oc@zhaoxin.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.32.56.37] X-ClientProxiedBy: ZXSHCAS1.zhaoxin.com (10.28.252.161) To zxbjmbx1.zhaoxin.com (10.29.252.163) Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2. On platforms with Zhaoxin CPUs supporting this X86 feature, when crc32c-intel and crc32c-generic are both registered, system will use crc32c-intel because its .cra_priority is greater than crc32c-generic. When doing lmbench3 Create and Delete file test on partitions with ext4 enabling metadata checksum, found using crc32c-generic driver could get about 20% performance gain than using the driver crc32c-intel on some Zhaoxin CPUs. Lower-level testing result is that with the same input value the generic C implementation takes fewer time than the crc32c instruction implementation on these CPUs. This case expect to use crc32c-generic driver for these CPUs to get performance gain. The presence of crc32c is enumerated by CPUID.01:ECX[SSE4.2] = 1, and these CPUs other SSE4.2 instructions is ok. Add a synthetic flag to indicates low performance CRC32C instruction implementation, set this flag in Zhaoxin CPUs specific init phase, and exclude CPUs which setting this flag from the driver crc32c-intel. https://lkml.org/lkml/2020/12/21/789 Tony W Wang-oc (3): x86/cpufeatures: Add low performance CRC32C instruction CPU feature x86/cpu: Set low performance CRC32C flag on some Zhaoxin CPUs crypto: x86/crc32c-intel Exclude low performance CRC32C instruction CPUs arch/x86/crypto/crc32c-intel_glue.c | 5 +++++ arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/centaur.c | 7 +++++++ arch/x86/kernel/cpu/cpuid-deps.c | 1 + arch/x86/kernel/cpu/zhaoxin.c | 6 ++++++ 5 files changed, 20 insertions(+) -- 2.7.4