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Subject: Re: [PATCH v1 2/3] x86/cpu: Set low performance CRC32C flag on some
 Zhaoxin CPUs
To:     Dave Hansen <dave.hansen@intel.com>, <herbert@gondor.apana.org.au>,
        <davem@davemloft.net>, <tglx@linutronix.de>, <mingo@redhat.com>,
        <bp@alien8.de>, <x86@kernel.org>, <hpa@zytor.com>,
        <tony.luck@intel.com>, <seanjc@google.com>, <fenghua.yu@intel.com>,
        <thomas.lendacky@amd.com>, <kyung.min.park@intel.com>,
        <kim.phillips@amd.com>, <mgross@linux.intel.com>,
        <peterz@infradead.org>, <krish.sadhukhan@oracle.com>,
        <liam.merwick@oracle.com>, <mlevitsk@redhat.com>,
        <reinette.chatre@intel.com>, <babu.moger@amd.com>,
        <linux-crypto@vger.kernel.org>, <linux-kernel@vger.kernel.org>
CC:     <TimGuo-oc@zhaoxin.com>, <CooperYan@zhaoxin.com>,
        <QiyuanWang@zhaoxin.com>, <HerryYang@zhaoxin.com>,
        <CobeChen@zhaoxin.com>, <SilviaZhao@zhaoxin.com>
References: <1610000348-17316-1-git-send-email-TonyWWang-oc@zhaoxin.com>
 <1610000348-17316-3-git-send-email-TonyWWang-oc@zhaoxin.com>
 <607494aa-674a-fe93-50f6-2c45f385f7e9@intel.com>
From:   Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Message-ID: <6d2f1d21-635d-d359-ee2c-ce0665f519d7@zhaoxin.com>
Date:   Mon, 11 Jan 2021 18:54:12 +0800
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On 07/01/2021 23:52, Dave Hansen wrote:
> On 1/6/21 10:19 PM, Tony W Wang-oc wrote:
>> +	/*
>> +	 * These CPUs declare support SSE4.2 instruction sets but
>> +	 * having low performance CRC32C instruction implementation.
>> +	 */
>> +	if (c->x86 == 0x6 || (c->x86 == 0x7 && c->x86_model <= 0x3b))
>> +		set_cpu_cap(c, X86_FEATURE_CRC32C);
>>  }
> 
> On the Intel side, we've tried to move away from open-coded model
> numbers.  Say another CPU is released that has a microarchitecture close
> to 0x3b, but has a model of 0x3c.  It's a *LOT* easier to grep for
> INTEL_FAM6_NEHALEM (or whatever) than 0x3c.  See:
> 
> 	arch/x86/include/asm/intel-family.h
> 
> for examples.
> .
> 

Got it, thanks for your suggestion.

Sincerely
Tonyw