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Date:   Mon, 11 Jan 2021 07:20:25 -0800
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Subject: Re: [PATCH v1 1/3] x86/cpufeatures: Add low performance CRC32C instruction CPU feature
To:     Borislav Petkov <bp@alien8.de>,
        Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
CC:     herbert@gondor.apana.org.au, davem@davemloft.net,
        tglx@linutronix.de, mingo@redhat.com, x86@kernel.org,
        tony.luck@intel.com, dave.hansen@intel.com, seanjc@google.com,
        fenghua.yu@intel.com, thomas.lendacky@amd.com,
        kyung.min.park@intel.com, kim.phillips@amd.com,
        mgross@linux.intel.com, peterz@infradead.org,
        krish.sadhukhan@oracle.com, liam.merwick@oracle.com,
        mlevitsk@redhat.com, reinette.chatre@intel.com, babu.moger@amd.com,
        linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org,
        TimGuo-oc@zhaoxin.com, CooperYan@zhaoxin.com,
        QiyuanWang@zhaoxin.com, HerryYang@zhaoxin.com,
        CobeChen@zhaoxin.com, SilviaZhao@zhaoxin.com
From:   hpa@zytor.com
Message-ID: <A96ECD10-F51F-408C-80DF-5937DF43D314@zytor.com>
Precedence: bulk

On January 6, 2021 10:37:50 PM PST, Borislav Petkov <bp@alien8=2Ede> wrote:
>On Thu, Jan 07, 2021 at 02:19:06PM +0800, Tony W Wang-oc wrote:
>> SSE4=2E2 on Zhaoxin CPUs are compatible with Intel=2E The presence of
>> CRC32C instruction is enumerated by CPUID=2E01H:ECX=2ESSE4_2[bit 20] =
=3D 1=2E
>> Some Zhaoxin CPUs declare support SSE4=2E2 instruction sets but their
>> CRC32C instruction are working with low performance=2E
>>=20
>> Add a synthetic CPU flag to indicates that the CRC32C instruction is
>> not working as intended=2E This low performance CRC32C instruction flag
>> is depend on X86_FEATURE_XMM4_2=2E
>>=20
>> Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin=2Ecom>
>> ---
>>  arch/x86/include/asm/cpufeatures=2Eh | 1 +
>>  arch/x86/kernel/cpu/cpuid-deps=2Ec   | 1 +
>>  2 files changed, 2 insertions(+)
>>=20
>> diff --git a/arch/x86/include/asm/cpufeatures=2Eh
>b/arch/x86/include/asm/cpufeatures=2Eh
>> index 84b8878=2E=2E9e8151b 100644
>> --- a/arch/x86/include/asm/cpufeatures=2Eh
>> +++ b/arch/x86/include/asm/cpufeatures=2Eh
>> @@ -292,6 +292,7 @@
>>  #define X86_FEATURE_FENCE_SWAPGS_KERNEL	(11*32+ 5) /* "" LFENCE in
>kernel entry SWAPGS path */
>>  #define X86_FEATURE_SPLIT_LOCK_DETECT	(11*32+ 6) /* #AC for split
>lock */
>>  #define X86_FEATURE_PER_THREAD_MBA	(11*32+ 7) /* "" Per-thread
>Memory Bandwidth Allocation */
>> +#define X86_FEATURE_CRC32C		(11*32+ 8) /* "" Low performance CRC32C
>instruction */
>
>Didn't hpa say to create a BUG flag for it - X86_BUG=2E=2E=2E? Low
>performance
>insn sounds like a bug and not a feature to me=2E
>
>And call it X86_BUG_CRC32C_SLOW or =2E=2E=2E_UNUSABLE to denote what it
>means=2E
>
>Thx=2E

Yes, it should be a BUG due to the inclusion properties of BUG v FEATURE=
=2E
--=20
Sent from my Android device with K-9 Mail=2E Please excuse my brevity=2E