Received: by 2002:a05:6a10:8c0a:0:0:0:0 with SMTP id go10csp1821752pxb; Mon, 18 Jan 2021 00:19:40 -0800 (PST) X-Google-Smtp-Source: ABdhPJxqh+vcGpgiNx5k6ju7hlyq0Zi+OztnfOWfr/FuZ3Es7NBXTFMgc62yDMae69uF93z+vSwq X-Received: by 2002:a17:906:ae4a:: with SMTP id lf10mr5800294ejb.480.1610957980450; Mon, 18 Jan 2021 00:19:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610957980; cv=none; d=google.com; s=arc-20160816; b=JgbeFYdGI65+Sedrf3o5H7RIU3c9hQS7xNou8UHVCBDUYuvgANahdcTdyxJLetB2eh 86FV9CPNbdfoHeyper8AHFr3ec5Fq0cV5VgDfi3UVeEpwOVhvZIfF8K9gIz2TsRB6DYv 8AiBvIVlFCUoQyW0ZF+TkD0DJOc+mDFpZ2UeRuZb0hDzWM02x92iuFiER6JjluTIhrtx kUlpayhKyLSlfJdpAZ0ORH7pnc6X0QqS46JoxedmcVeMDtBTGLGJzVDIXcpRDbhYT+e6 qo8AXW96A2VNmMQC0j8drEklWXI1IEtGQxmx2X9FtiyVAuFus8Dj/1usyx4T/1fW4vs+ l3IQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:message-id:date:subject:cc:to:from; bh=dVYdzkFYcnHRkHbfmuc9jQwn47Agqka3KqTiC2q39C8=; b=H3wldJHQgm1h+AP7w9+At3jYa22yyoWjj9aVhJJntclCyypNJ4vfxtR39YYJlMUVqM 6IF2JIF7b1BMBbQZKaYh2TI5tnrJO60LpoThnuqx/r7zbWHs6givmQb4Q6O0JHCxi/4Z H0OKbD/bI3vfzABFgHgSNQl56IVythRERGV4gOhHoqqyxH/29TG3BZ/7dbU9tBDNil4e o6BBXMw0+0F0BNyn8f/37KyEXMrBugquaODiXXsvczwnx1HAqzPEn51A1NPv8pFSRCwq Y2mV5MkP7dPe8rMEsb2Kut7lfYNEHWHtEBTcVdP5Ps5T3HvAqiAZ110Inl0ZaQXicSJX wroQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id n7si6830287ejx.635.2021.01.18.00.19.20; Mon, 18 Jan 2021 00:19:40 -0800 (PST) Received-SPF: pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387600AbhARISe (ORCPT + 99 others); Mon, 18 Jan 2021 03:18:34 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:11107 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387572AbhARISd (ORCPT ); Mon, 18 Jan 2021 03:18:33 -0500 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4DK4Pn3LNNz15vKw; Mon, 18 Jan 2021 16:16:45 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.498.0; Mon, 18 Jan 2021 16:17:44 +0800 From: Hui Tang To: , CC: , , , , Subject: [PATCH] crypto: hisilicon/hpre - delete ECC 1bit error reported threshold Date: Mon, 18 Jan 2021 16:15:40 +0800 Message-ID: <1610957740-2989-1-git-send-email-tanghui20@huawei.com> X-Mailer: git-send-email 2.8.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Delete 'HPRE_RAS_ECC1BIT_TH' register setting of hpre, since register 'QM_RAS_CE_THRESHOLD' of qm has done this work. Signed-off-by: Hui Tang Reviewed-by: Zaibo Xu --- drivers/crypto/hisilicon/hpre/hpre_main.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c b/drivers/crypto/hisilicon/hpre/hpre_main.c index ad8b691..bf1fa08 100644 --- a/drivers/crypto/hisilicon/hpre/hpre_main.c +++ b/drivers/crypto/hisilicon/hpre/hpre_main.c @@ -36,7 +36,6 @@ #define HPRE_INT_STATUS 0x301800 #define HPRE_CORE_INT_ENABLE 0 #define HPRE_CORE_INT_DISABLE 0x003fffff -#define HPRE_RAS_ECC_1BIT_TH 0x30140c #define HPRE_RDCHN_INI_ST 0x301a00 #define HPRE_CLSTR_BASE 0x302000 #define HPRE_CORE_EN_OFFSET 0x04 @@ -312,7 +311,6 @@ static int hpre_set_user_domain_and_cache(struct hisi_qm *qm) writel(HPRE_QM_VFG_AX_MASK, HPRE_ADDR(qm, HPRE_VFG_AXCACHE)); writel(0x0, HPRE_ADDR(qm, HPRE_BD_ENDIAN)); writel(0x0, HPRE_ADDR(qm, HPRE_INT_MASK)); - writel(0x0, HPRE_ADDR(qm, HPRE_RAS_ECC_1BIT_TH)); writel(0x0, HPRE_ADDR(qm, HPRE_POISON_BYPASS)); writel(0x0, HPRE_ADDR(qm, HPRE_COMM_CNT_CLR_CE)); writel(0x0, HPRE_ADDR(qm, HPRE_ECC_BYPASS)); -- 2.8.1