Received: by 2002:a05:6a10:17d3:0:0:0:0 with SMTP id hz19csp1760063pxb; Mon, 12 Apr 2021 06:13:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzK2eab2Fg54DEsfPnmApT3/+YuFUkXcuNMaMifj2ZRzo+0q8Y09g5pL5ydVVnk+F1TTXF8 X-Received: by 2002:a62:76cf:0:b029:241:ba8d:eac1 with SMTP id r198-20020a6276cf0000b0290241ba8deac1mr24774268pfc.71.1618233198257; Mon, 12 Apr 2021 06:13:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618233198; cv=none; d=google.com; s=arc-20160816; b=fI6rYLPBOcivM9RHtehxeftWmnGGHxt7VXcm0V7597Nqcno51MWe+ZET/dYbtVx3Xa kOp3y7McWgPuhundMFPIBiJMK2lvTVrGyulQcZCmLeVvD0dmooz56iiMpp62ggZHg6UM YaZDtutIrYG1/cgr9psYZDiU4zl8znV/0nRE05EyvMGKi+iA1UsERbcyzZpWKkaGfjig zUoO33fEf7VZhfuN+VDCucUNWQ2OnNmYYe9C8S1NYaKJzdMUikNmxDn5KGBXa0VxfY/E yoM7vLDPcHrZoTusBKdqui2XTL452GjoN+1h9mFSSpcNQpaCExcF5Z+A56I1cuY3mGqh g/0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=KEu8l+x8kdU6SE8gW05vx8Dm1nMAqA+qoUbk3y4APEA=; b=LMIHTMo98907zcWNgKNm24dwjQzFFpQMUMv+IKtqehkFpknfSK6I5E3XwFey3wGaoI VZXVhLtTZIwsEZmdp8BCr/xfpDVc5jA180Z0SCFKkVgHnQggU0E7TTrAd3rd+BN4EeSE 9ZKtX3TFCbarTl+lNg50iUiyntEn6tPzP8wNcY8Fk67hDICbRtJdQ7D/a5lYBU4OBZ7r nLSTCAnuhqHLBzZseLXzRLICwfUY07nJN7D91rIDKJRRnl4toJu02GijbQmnve6XnM2z 4Wyt/br7txnx7/uaro98zC3J45Flqhg0tb4dBv6w2eRs7G1d1CUWGNdOSfOXHK62AWwi HRhA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id x10si13984551pjl.5.2021.04.12.06.12.48; Mon, 12 Apr 2021 06:13:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241897AbhDLNMY (ORCPT + 99 others); Mon, 12 Apr 2021 09:12:24 -0400 Received: from mail.kernel.org ([198.145.29.99]:36842 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241722AbhDLNMV (ORCPT ); Mon, 12 Apr 2021 09:12:21 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 49B446128A; Mon, 12 Apr 2021 13:12:01 +0000 (UTC) From: Catalin Marinas To: linux-crypto@vger.kernel.org, Ard Biesheuvel Cc: Will Deacon , Catalin Marinas , Sebastian Andrzej Siewior , Dave Martin , Peter Zijlstra , Eric Biggers , Ingo Molnar , Mark Brown , Herbert Xu , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Andy Lutomirski Subject: Re: (subset) [PATCH v2 0/9] running kernel mode SIMD with softirqs disabled Date: Mon, 12 Apr 2021 14:11:13 +0100 Message-Id: <161822613829.4133.7312323262518323547.b4-ty@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210302090118.30666-1-ardb@kernel.org> References: <20210302090118.30666-1-ardb@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org On Tue, 2 Mar 2021 10:01:09 +0100, Ard Biesheuvel wrote: > [ TL;DR for the non-ARM folks on CC: disabling softirq processing when using > SIMD in kernel mode could reduce complexity and improve performance, but we > need to decide whether we can do this, and how much softirq processing > latency we can tolerate. If we can find a satisfactory solution for this, > we might do the same for x86 and 32-bit ARM as well. > > However, based on preliminary off-list discussions with peterz and luto, it > seems that for x86, there is a preference for using per-CPU buffers to > preserve/restore the task context's kernel mode SIMD state when the task is > interrupted to perform kernel mode SIMD in softirq context. On arm64, we > actually had this arrangement before, and removed it because it made > reasoning about preserving/restoring userland SVE state (32 SIMD registers > of up to 2 kbit in size) rather complex. ] > > [...] Applied to arm64 (for-next/neon-softirqs-disabled), thanks! [1/9] arm64: assembler: remove conditional NEON yield macros https://git.kernel.org/arm64/c/27248fe1abb2 [2/9] arm64: assembler: introduce wxN aliases for wN registers https://git.kernel.org/arm64/c/4c4dcd3541f8 [3/9] arm64: fpsimd: run kernel mode NEON with softirqs disabled https://git.kernel.org/arm64/c/13150149aa6d -- Catalin