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[23.128.96.18]) by mx.google.com with ESMTP id q4si11755138ils.118.2021.08.02.03.40.57; Mon, 02 Aug 2021 03:41:17 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=aHzmvqtc; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233167AbhHBKlE (ORCPT + 99 others); Mon, 2 Aug 2021 06:41:04 -0400 Received: from mail.kernel.org ([198.145.29.99]:38028 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231854AbhHBKlD (ORCPT ); Mon, 2 Aug 2021 06:41:03 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 2B92060F9E; Mon, 2 Aug 2021 10:40:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1627900854; bh=DSvgIx4J8JKOg4XXggMVa7s1UrkqGDWBAGiVCWCSJ4I=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=aHzmvqtcEqLSPKqPm3+sAmkHab6hc7Lq6m3VR1X5GlwJzz995Dx7KneRxEuU/SDcc kZTGSj4U3lXFkEDPsoU8yrtRdulO8dguNtU4tPI/QwgIo87U+MNjC70t9wLdodwYf8 kOgwHhv8ZTIPApwMnspvIu8B+WS8i3RXEXJjSJ6s90g+2GLT6RZjsHiON4Y6zy+Ljr 0BdzHzlSM2HUl4jLAkHtFG8EvTRlJevScSITi4l7hfxeZ3Cq/PW2It7dUvM9iPEv4e xm+KqVVmBf4LEZHvGbHXdxUEHQ3sGhiZnl4BsH90z4/Kfub4lUWSOcHoCbjuEyxcPP fxZkeMq87satg== Date: Mon, 2 Aug 2021 11:40:40 +0100 From: Mark Brown To: Andre Przywara Cc: Matt Mackall , Herbert Xu , Mark Rutland , Lorenzo Pieralisi , Sudeep Holla , linux-crypto@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Herrenschmidt , Ard Biesheuvel , Will Deacon , Ali Saidi , Jon Nettleton Subject: Re: [PATCH v4 0/2] hwrng: Add Arm SMCCC TRNG based driver Message-ID: <20210802104040.GA4668@sirena.org.uk> References: <20210731204845.21196-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="IS0zKkzwUGydFO0o" Content-Disposition: inline In-Reply-To: <20210731204845.21196-1-andre.przywara@arm.com> X-Cookie: There's only one everything. User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org --IS0zKkzwUGydFO0o Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Sat, Jul 31, 2021 at 09:48:43PM +0100, Andre Przywara wrote: > The "Arm True Random Number Generator Firmware Interface"[1] provides > an SMCCC based interface to a true hardware random number generator. > So far we are using that in arch_get_random_seed(), but it might be > useful to expose the entropy through the /dev/hwrng device as well. This > allows to assess the quality of the implementation, by using "rngtest" > from the rng-tools package, for example. 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