Received: by 2002:a05:6a10:8a4d:0:0:0:0 with SMTP id dn13csp179740pxb; Thu, 12 Aug 2021 13:45:29 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyjBZz8tkPOF5UQGKtya2krzNdjAmCaMKQG1ly0uSiZCwgaXIqG32uEeEo7hz+4RTNFpCr+ X-Received: by 2002:a17:906:1e42:: with SMTP id i2mr5586754ejj.76.1628801129501; Thu, 12 Aug 2021 13:45:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1628801129; cv=none; d=google.com; s=arc-20160816; b=nT17gy07TTaL18lc+yq/WWeeh26SxNz/4KfMq3WezCqUvxMG1EvwLk2Ikqmxhl34yV npli6hRUxeSYPX2YPt+YNlD7yof2pQpoRyJ9hY1Uo1UFehNFNy8hhFCKFsKaWpAiDlxm f3LjTygsIgC1Zg1W/CNO75W3WA/ke7Br4G32wlQdARPRvcUiMW9ziRD17hAhWiQFNJ7a 3xh3TPs+0XrGGHtlleV4Bthgd4+KA7Vtb4z9/gSEzTg4W/zy07FsJql3af//69RDL3Er UENgVwT26pr8FU9IcTdIe/hhLVjtVqU71jM+M4parCh5JSTvdZP9+NHtWvACt7MpQjRY wqEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:organization :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from; bh=ObDjxf8hNVbvNtBqedgkGtICSMFgVf4zUTmOfc+UTeA=; b=UlUfc9g5DFcbwBZ2ItbsUMJZuP9TUtgUk8CaKGhG3yYCCYXJKbLddxWs5MBZ2IbdBR YUNyxQJACSUuIs+2QbojYw6jDobKKPw2fzA1mmpwuemPQmL8mO/nDDfZnJCrYXMVxrnB f1yyJgyo9Shi8mGm3QZZQe5Tuc63yEYEPXvqvUP9w91VMkcB9NxNZlF1ojJCmmFyZlJa jIR5CkoHEzCP3p3hcHJkT9vecdCuNRANO2Vtx5gdbWRPhqVveQKWeAFVE+HKJc9EzzH5 f1PGMNj67DJJcd/RKj9fNXya/GAvk/oGqBQzE3AJffI08xMS4uLd/qn1TEiAxN5DrMSe iaIw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id p12si3780206ejj.2.2021.08.12.13.45.05; Thu, 12 Aug 2021 13:45:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234909AbhHLUWZ (ORCPT + 99 others); Thu, 12 Aug 2021 16:22:25 -0400 Received: from mga03.intel.com ([134.134.136.65]:4151 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236922AbhHLUWV (ORCPT ); Thu, 12 Aug 2021 16:22:21 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10074"; a="215474018" X-IronPort-AV: E=Sophos;i="5.84,316,1620716400"; d="scan'208";a="215474018" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 13:21:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,316,1620716400"; d="scan'208";a="517608579" Received: from silpixa00400314.ir.intel.com (HELO silpixa00400314.ger.corp.intel.com) ([10.237.222.51]) by FMSMGA003.fm.intel.com with ESMTP; 12 Aug 2021 13:21:46 -0700 From: Giovanni Cabiddu To: herbert@gondor.apana.org.au Cc: linux-crypto@vger.kernel.org, qat-linux@intel.com, Giovanni Cabiddu , Marco Chiappero , Fiona Trahe Subject: [PATCH 05/20] crypto: qat - handle both source of interrupt in VF ISR Date: Thu, 12 Aug 2021 21:21:14 +0100 Message-Id: <20210812202129.18831-6-giovanni.cabiddu@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210812202129.18831-1-giovanni.cabiddu@intel.com> References: <20210812202129.18831-1-giovanni.cabiddu@intel.com> MIME-Version: 1.0 Organization: Intel Research and Development Ireland Ltd - Co. Reg. #308263 - Collinstown Industrial Park, Leixlip, County Kildare - Ireland Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org The top half of the VF drivers handled only a source at the time. If an interrupt for PF2VF and bundle occurred at the same time, the ISR scheduled only the bottom half for PF2VF. This patch fixes the VF top half so that if both sources of interrupt trigger at the same time, both bottom halves are scheduled. This patch is based on earlier work done by Conor McLoughlin. Signed-off-by: Giovanni Cabiddu Reviewed-by: Marco Chiappero Reviewed-by: Fiona Trahe --- drivers/crypto/qat/qat_common/adf_vf_isr.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/crypto/qat/qat_common/adf_vf_isr.c b/drivers/crypto/qat/qat_common/adf_vf_isr.c index 888388acb6bd..3e4f64d248f9 100644 --- a/drivers/crypto/qat/qat_common/adf_vf_isr.c +++ b/drivers/crypto/qat/qat_common/adf_vf_isr.c @@ -160,6 +160,7 @@ static irqreturn_t adf_isr(int irq, void *privdata) struct adf_bar *pmisc = &GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)]; void __iomem *pmisc_bar_addr = pmisc->virt_addr; + bool handled = false; u32 v_int; /* Read VF INT source CSR to determine the source of VF interrupt */ @@ -172,7 +173,7 @@ static irqreturn_t adf_isr(int irq, void *privdata) /* Schedule tasklet to handle interrupt BH */ tasklet_hi_schedule(&accel_dev->vf.pf2vf_bh_tasklet); - return IRQ_HANDLED; + handled = true; } /* Check bundle interrupt */ @@ -184,10 +185,10 @@ static irqreturn_t adf_isr(int irq, void *privdata) csr_ops->write_csr_int_flag_and_col(bank->csr_addr, bank->bank_number, 0); tasklet_hi_schedule(&bank->resp_handler); - return IRQ_HANDLED; + handled = true; } - return IRQ_NONE; + return handled ? IRQ_HANDLED : IRQ_NONE; } static int adf_request_msi_irq(struct adf_accel_dev *accel_dev) -- 2.31.1