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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id d26sm781598oos.41.2021.08.17.18.20.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Aug 2021 18:20:32 -0700 (PDT) Received: (nullmailer pid 1182736 invoked by uid 1000); Wed, 18 Aug 2021 01:20:30 -0000 Date: Tue, 17 Aug 2021 20:20:30 -0500 From: Rob Herring To: Sam Shih Cc: linux-clk@vger.kernel.org, Stephen Boyd , linux-kernel@vger.kernel.org, Greg Kroah-Hartman , linux-watchdog@vger.kernel.org, Herbert Xu , linux-serial@vger.kernel.org, Sean Wang , linux-gpio@vger.kernel.org, Linus Walleij , Hsin-Yi Wang , Rob Herring , linux-mediatek@lists.infradead.org, Enric Balletbo i Serra , Wim Van Sebroeck , Fabien Parent , linux-crypto@vger.kernel.org, Matt Mackall , Matthias Brugger , linux-arm-kernel@lists.infradead.org, John Crispin , Ryder Lee , Seiya Wang , devicetree@vger.kernel.org, Guenter Roeck , Michael Turquette Subject: Re: [v2,02/12] clk: mediatek: add mt7986 clock IDs Message-ID: References: <20210817074557.30953-1-sam.shih@mediatek.com> <20210817074557.30953-3-sam.shih@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210817074557.30953-3-sam.shih@mediatek.com> Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org On Tue, 17 Aug 2021 15:45:47 +0800, Sam Shih wrote: > Add MT7986 clock dt-bindings, include topckgen, apmixedsys, > infracfg, and ethernet subsystem clocks. > > Signed-off-by: Sam Shih > > --- > v2: changed to dual licience > applied the comment suggested by reviewers: > - removed 1:1 factor clock > - renamed factor clock for easier to understand > > --- > include/dt-bindings/clock/mt7986-clk.h | 169 +++++++++++++++++++++++++ > 1 file changed, 169 insertions(+) > create mode 100644 include/dt-bindings/clock/mt7986-clk.h > Acked-by: Rob Herring