Received: by 2002:a05:6a11:4021:0:0:0:0 with SMTP id ky33csp481100pxb; Tue, 14 Sep 2021 01:53:24 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzkPJrGKyrbEq4uU0V1hPu67XiNezlbPd6WuRxkniL3WMiadqI6zifvYYxxK4LeCU7iuC+r X-Received: by 2002:a92:cbc2:: with SMTP id s2mr10958829ilq.228.1631609604547; Tue, 14 Sep 2021 01:53:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1631609604; cv=none; d=google.com; s=arc-20160816; b=KyJUSjatzuShrlN6kv6fOKFLxXD9Wf5gG42eJgYOgq18Rn9kLPcBMhGspBdT2GLqFo 7Wt8rMBblxEYjMfKHktSJRX4S3B8a9/wLTH5Irfy+jn2fUfHBUSl0H/ON/q4UXIoXAb3 kGNyFficvJ1lXUpZfqiZIiOTQMYdM/JFYZcJpuGoY0LPhOKD/qIBHM2QgYk3V0+XtPaA Hy2YZMOwpA6gPFixIVSfkRZAZkvokUPzOqLT17jrEswxMXEgv3Z+ypIV7aikzlhLgRLx 0rUj6SENXBw9PX2MhpF1tYW1kLZ/4I9ug/B8zpQmX7dZ5uL/eyE8eDx231rr1YKU02+l 9VyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=y7BNRyByVzTUHEMPoRolFIv3opgDCZNn9B9BvCs9TAE=; b=SPKjO5F6n6yShcD5ALFdjLSSrHG5Dk0+WwRX+8v8Qpiy/VhfliC9aqDboMnwUCg7+c mqXrds6dagMqJOgNBnY1zTstybBXPnJVnMMpuB27ng2HRUhAfoKKJ1KBj7AnpdAUBEAA FMjvf2vmkNRBMK/VQgJ3OfgD9n2sjsf1sGfkfebf0hG8F0BaPER6Vd0NPpUg+4rIaXL0 q8xzfbMeXVF8XP6pS1MOmWFqOWt6eEiGZyQiZ2BuIf3YT6618HBM3fo3ZVx+9EoVSXC9 924JRAm2sqvDjDwPKQ+BHqmJbWp3xCwi1F/4LqDumogs9JKfMQR6WPgbem0hSzovtQXb RUVQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id m1si8439064jaa.128.2021.09.14.01.53.12; Tue, 14 Sep 2021 01:53:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231698AbhINIyS (ORCPT + 99 others); Tue, 14 Sep 2021 04:54:18 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:51316 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231463AbhINIyG (ORCPT ); Tue, 14 Sep 2021 04:54:06 -0400 X-UUID: 3ffd3b946d484004b95cd2b73b9e7fd2-20210914 X-UUID: 3ffd3b946d484004b95cd2b73b9e7fd2-20210914 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1515088546; Tue, 14 Sep 2021 16:52:46 +0800 Received: from mtkmbs10n1.mediatek.inc (172.21.101.34) by mtkmbs06n2.mediatek.inc (172.21.101.130) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 14 Sep 2021 16:52:45 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Tue, 14 Sep 2021 16:52:45 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 14 Sep 2021 16:52:44 +0800 From: Sam Shih To: Rob Herring , Sean Wang , "Linus Walleij" , Matthias Brugger , Matt Mackall , Herbert Xu , Greg Kroah-Hartman , Wim Van Sebroeck , Guenter Roeck , Michael Turquette , Stephen Boyd , Hsin-Yi Wang , Enric Balletbo i Serra , Fabien Parent , Seiya Wang , , , , , , , , , CC: John Crispin , Ryder Lee , "Sam Shih" Subject: [RESEND,v3,4/9] pinctrl: mediatek: moore: check if pin_desc is valid before use Date: Tue, 14 Sep 2021 16:51:32 +0800 Message-ID: <20210914085137.31761-5-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210914085137.31761-1-sam.shih@mediatek.com> References: <20210914085137.31761-1-sam.shih@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Certain SoC are missing the middle part gpios in consecutive pins, it's better to check if mtk_pin_desc is a valid pin for the extensibility Signed-off-by: Sam Shih Acked-by: Sean Wang --- v3: added an Acked-by tag. v2: applied the comment suggested by reviewers: - for the pins not ballout, we can fill .name in struct mtk_pin_desc as NULL and return -ENOTSUPP in gpio/pinconf ops. --- drivers/pinctrl/mediatek/pinctrl-moore.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c index 3a4a23c40a71..ad3b67163973 100644 --- a/drivers/pinctrl/mediatek/pinctrl-moore.c +++ b/drivers/pinctrl/mediatek/pinctrl-moore.c @@ -60,6 +60,8 @@ static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev, int pin = grp->pins[i]; desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; + if (!desc->name) + return -ENOTSUPP; mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, pin_modes[i]); @@ -76,6 +78,8 @@ static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, const struct mtk_pin_desc *desc; desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; + if (!desc->name) + return -ENOTSUPP; return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, hw->soc->gpio_m); @@ -89,6 +93,8 @@ static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, const struct mtk_pin_desc *desc; desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; + if (!desc->name) + return -ENOTSUPP; /* hardware would take 0 as input direction */ return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input); @@ -103,6 +109,8 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, const struct mtk_pin_desc *desc; desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; + if (!desc->name) + return -ENOTSUPP; switch (param) { case PIN_CONFIG_BIAS_DISABLE: @@ -218,6 +226,8 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, int cfg, err = 0; desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; + if (!desc->name) + return -ENOTSUPP; for (cfg = 0; cfg < num_configs; cfg++) { param = pinconf_to_config_param(configs[cfg]); @@ -435,6 +445,8 @@ static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio) int value, err; desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; + if (!desc->name) + return -ENOTSUPP; err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value); if (err) @@ -449,6 +461,10 @@ static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) const struct mtk_pin_desc *desc; desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; + if (!desc->name) { + dev_err(hw->dev, "Failed to set gpio %d\n", gpio); + return; + } mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value); } @@ -490,6 +506,8 @@ static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset, u32 debounce; desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset]; + if (!desc->name) + return -ENOTSUPP; if (!hw->eint || pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE || -- 2.29.2