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[62.248.207.242]) by smtp.gmail.com with ESMTPSA id y6sm1327449lfa.122.2021.10.13.06.05.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 Oct 2021 06:05:17 -0700 (PDT) Subject: Re: [PATCH v4 07/20] dt-bindings: qcom-qce: Convert bindings to yaml To: Bhupesh Sharma , linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org Cc: bhupesh.linux@gmail.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, agross@kernel.org, herbert@gondor.apana.org.au, davem@davemloft.net, Thara Gopinath , Bjorn Andersson , Rob Herring References: <20211013105541.68045-1-bhupesh.sharma@linaro.org> <20211013105541.68045-8-bhupesh.sharma@linaro.org> From: Vladimir Zapolskiy Message-ID: Date: Wed, 13 Oct 2021 16:05:17 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.1 MIME-Version: 1.0 In-Reply-To: <20211013105541.68045-8-bhupesh.sharma@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Hi Bhupesh, On 10/13/21 1:55 PM, Bhupesh Sharma wrote: > Convert Qualcomm QCE crypto devicetree binding to YAML. > > Cc: Thara Gopinath > Cc: Bjorn Andersson > Reviewed-by: Rob Herring > Signed-off-by: Bhupesh Sharma > --- > .../devicetree/bindings/crypto/qcom-qce.yaml | 67 +++++++++++++++++++ > 1 file changed, 67 insertions(+) > create mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.yaml > > diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml > new file mode 100644 > index 000000000000..b7ae873dc943 > --- /dev/null > +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml > @@ -0,0 +1,67 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm crypto engine driver > + > +maintainers: > + - Bhupesh Sharma > + > +description: | > + This document defines the binding for the QCE crypto > + controller found on Qualcomm parts. > + > +properties: > + compatible: > + const: qcom,crypto-v5.1 > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: iface clocks register interface. > + - description: bus clocks data transfer interface. > + - description: core clocks rest of the crypto block. > + > + clock-names: > + items: > + - const: iface > + - const: bus > + - const: core > + > + dmas: > + items: > + - description: DMA specifiers for tx dma channel. > + - description: DMA specifiers for rx dma channel. Please consider to swap the description lines, so that they'll be matching the dma-names below and a regular order found in dts files. > + > + dma-names: > + items: > + - const: rx > + - const: tx > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - dmas > + - dma-names > + > +additionalProperties: false > + > +examples: > + - | > + #include > + crypto-engine@fd45a000 { > + compatible = "qcom,crypto-v5.1"; > + reg = <0xfd45a000 0x6000>; > + clocks = <&gcc GCC_CE2_AHB_CLK>, > + <&gcc GCC_CE2_AXI_CLK>, > + <&gcc GCC_CE2_CLK>; > + clock-names = "iface", "bus", "core"; > + dmas = <&cryptobam 2>, <&cryptobam 3>; > + dma-names = "rx", "tx"; > + }; > -- Best wishes, Vladimir