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[89.77.68.124]) by smtp.gmail.com with ESMTPSA id bn17sm1751216ljb.22.2021.12.17.06.59.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Dec 2021 06:59:44 -0800 (PST) Message-ID: Date: Fri, 17 Dec 2021 15:59:42 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.3.1 Subject: Re: [PATCH v2 14/17] riscv: dts: microchip: add fpga fabric section to icicle kit Content-Language: en-US To: conor.dooley@microchip.com, linus.walleij@linaro.org, bgolaszewski@baylibre.com, robh+dt@kernel.org, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, a.zummo@towertech.it, alexandre.belloni@bootlin.com, broonie@kernel.org, gregkh@linuxfoundation.org, thierry.reding@gmail.com, u.kleine-koenig@pengutronix.de, lee.jones@linaro.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pwm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-crypto@vger.kernel.org, linux-rtc@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org Cc: geert@linux-m68k.org, bin.meng@windriver.com, heiko@sntech.de, lewis.hanly@microchip.com, daire.mcnamara@microchip.com, ivan.griffin@microchip.com, atish.patra@wdc.com References: <20211217093325.30612-1-conor.dooley@microchip.com> <20211217093325.30612-15-conor.dooley@microchip.com> From: Krzysztof Kozlowski In-Reply-To: <20211217093325.30612-15-conor.dooley@microchip.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org On 17/12/2021 10:33, conor.dooley@microchip.com wrote: > From: Conor Dooley > > Split the device tree for the Microchip MPFS into two sections by adding > microchip-mpfs-fabric.dtsi, which contains peripherals contained in the > FPGA fabric. > > Signed-off-by: Conor Dooley > --- > .../boot/dts/microchip/microchip-mpfs-fabric.dtsi | 13 +++++++++++++ > .../dts/microchip/microchip-mpfs-icicle-kit.dts | 4 ++++ > arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 1 + > 3 files changed, 18 insertions(+) > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi > > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi > new file mode 100644 > index 000000000000..234c1f9bea40 > --- /dev/null > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi > @@ -0,0 +1,13 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* Copyright (c) 2020-2021 Microchip Technology Inc */ > + > +/ { > + corePWM0: pwm@41000000 { Lowercase labels please, so could be "core_pwm0". Best regards, Krzysztof