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Peter Anvin" , Linux Crypto Mailing List , Herbert Xu , "David S. Miller" , "Ravi V. Shankar" , "Chen, Tim C" , "Kleen, Andi" , greg.b.tucker@intel.com, "Kasten, Robert A" , rajendrakumar.chinnaiyan@intel.com, tomasz.kantecki@intel.com, ryan.d.saffores@intel.com, ilya.albrekht@intel.com, Kyung Min Park , Weiny Ira , Eric Biggers , Ard Biesheuvel , X86 ML References: <1611386920-28579-1-git-send-email-megha.dey@intel.com> <3878af8d-ac1e-522a-7c9f-fda4a1f5b967@intel.com> From: Dave Hansen Subject: Re: [RFC V2 0/5] Introduce AVX512 optimized crypto algorithms In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org On 1/31/22 10:43, Dey, Megha wrote: > With this implementation, we see a 1.5X improvement on ICX/ICL for 16KB > buffers compared to the existing kernel AES-GCM implementation that > works on 128-bit XMM registers. What is your best guess about how future-proof this implementation is? Will this be an ICL/ICX one-off? Or, will implementations using 256-bit YMM registers continue to enjoy a frequency advantage over the 512-bit implementations for a long time?