Received: by 2002:a6b:500f:0:0:0:0:0 with SMTP id e15csp2141456iob; Thu, 5 May 2022 17:02:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwgAiFcwsxauFnyMqEKYEzqdW1SqaNUJlknBjrNowbsqzVRTod1Ffd5+ipVQSHJdJbFWBM1 X-Received: by 2002:a17:906:1e94:b0:6b9:6fcc:53fd with SMTP id e20-20020a1709061e9400b006b96fcc53fdmr622132ejj.450.1651795321541; Thu, 05 May 2022 17:02:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1651795321; cv=none; d=google.com; s=arc-20160816; b=qWmvcnHZWFMtWXmAlEn/QviIV7k9V2ZUsLXboUpRxBLwT1wM725wR0MkGeqlayOxuH Mgd8TWstScweLQ3COx9JQSf/st5XSjeR+CgTqMmpBYt4WT0M0xBh5FTYbf5xh0jZq88J 2W/IZGwOhsTJCrLf0IFvcw+WKRy7LjagqGdvb3hq2XncUJT3k2Eqby01Yu6Cu2sSI7He 5MYl7eL1HchSKd37hedoJnEvBWoBMLYAp0c+SjjS0/ot49gYkOZofQ5nAHOdCpUm320b eMxRZV0nFjVI6S5HkhXhP++jfByh9lfJmUMGJzs/f+Let8sNzm558pM6YtGdibXTjWVF 205Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date:dkim-signature; bh=+0yLBZFl2WW/Vmag/O0qklCz8vPzv+IqHojDxes0uU0=; b=FETrfy+kzXvIuHkfofb1r2er0ML8Q1xj8g7WjGZsg+92Ixf6TjeyntCdbA898qF3C4 qFFVhly8BKZ2jLx1Rf3waoMGwuVDTinjKjXRlI531LmyJAuC7HaCSCa7yhfIq9q/iBEB HMKuWRvvglR/d+f+r6Zf6EDcj6T/ZPIGUgO7WXOrxbjJzpxkr9F/8ylpgn8r1azINqnY qLGtYqHwJOohNCmcfIETzgMUZj9ig0MJB8Lcr3gUXcxUDFGLvxWutz9/7a9yx63UlrRk BkSzrKUBL5xy6LnksVhnqu53wlAHzl/M9gWlz30PJqFa7KFIl/E8RQ6mCoP55ZFjWbX4 eiKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=suSziVbV; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id x71-20020a50bacd000000b00423f40b8548si3045480ede.579.2022.05.05.17.01.21; Thu, 05 May 2022 17:02:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=suSziVbV; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237018AbiEEFMU (ORCPT + 99 others); Thu, 5 May 2022 01:12:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233854AbiEEFMS (ORCPT ); Thu, 5 May 2022 01:12:18 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A0DC21821; Wed, 4 May 2022 22:08:40 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id B3D9561ADE; Thu, 5 May 2022 05:08:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CAFC3C385A4; Thu, 5 May 2022 05:08:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1651727319; bh=lBK8/trxgvR1f4DEH1CbdWJ4Y+Fce8JnB+5d9H6RVS0=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=suSziVbVT9y/3fYePbKPNEptGZeRtOsVOFwhAm+gaQTOpu2HbcFR6CdEGNm3Xiolx wyDNW+cVr3bW8fUTb0JjVCKscsjlkrhj+3wLACt7cFD4CJnPVY0e/06E58IQPGkvQK 9cT2ALQqC8XuyuDB7peO/lCupdbzCR1f9c+ICnAWvYfjISd4PRYlms6y3xZU+ebN49 lUnnA44MyGDnvec6LYVkImKIQ1QaBr0mFFnlYenBI0LyovtQi/Ibue/gBtm0c7DeD/ WFHoN3v9CBjzjXKVv2OAG1EWSzDp+Y9dWbx2gylVnOvkdkC0EqhAdLQ9nowJyIzmKE pPMYQSOIw0MWA== Date: Wed, 4 May 2022 22:08:37 -0700 From: Eric Biggers To: Nathan Huckleberry Cc: linux-crypto@vger.kernel.org, linux-fscrypt@vger.kernel.org, Herbert Xu , "David S. Miller" , linux-arm-kernel@lists.infradead.org, Paul Crowley , Sami Tolvanen , Ard Biesheuvel Subject: Re: [PATCH v6 7/9] crypto: x86/polyval: Add PCLMULQDQ accelerated implementation of POLYVAL Message-ID: References: <20220504001823.2483834-1-nhuck@google.com> <20220504001823.2483834-8-nhuck@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220504001823.2483834-8-nhuck@google.com> X-Spam-Status: No, score=-7.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org On Wed, May 04, 2022 at 12:18:21AM +0000, Nathan Huckleberry wrote: > +.macro schoolbook1_iteration i xor_sum > + movups (16*\i)(MSG), %xmm0 > + .if (\i == 0 && \xor_sum == 1) > + pxor SUM, %xmm0 > + .endif > + vpclmulqdq $0x01, (16*\i)(KEY_POWERS), %xmm0, %xmm2 > + vpclmulqdq $0x00, (16*\i)(KEY_POWERS), %xmm0, %xmm1 > + vpclmulqdq $0x10, (16*\i)(KEY_POWERS), %xmm0, %xmm3 > + vpclmulqdq $0x11, (16*\i)(KEY_POWERS), %xmm0, %xmm4 > + vpxor %xmm2, MI, MI > + vpxor %xmm1, LO, LO > + vpxor %xmm4, HI, HI > + vpxor %xmm3, MI, MI > +.endm The 8 lines above are indented with spaces. They should use tabs, like everywhere else. > + * So our final computation is: T = T_1 : T_0 = g*(x) * P_0 V = V_1 : V_0 = > + * g*(x) * (P_1 + T_0) p(x) / x^{128} mod g(x) = P_3 + P_1 + T_0 + V_1 : P_2 + > + * P_0 + T_1 + V_0 This part is unreadable now -- it looks like you formatted it as regular text? The three equations should be on their own lines, like how it was before. > +__maybe_unused static const struct x86_cpu_id pcmul_cpu_id[] = { > + X86_MATCH_FEATURE(X86_FEATURE_PCLMULQDQ, NULL), > + X86_MATCH_FEATURE(X86_FEATURE_AVX, NULL), > + {} > +}; > +MODULE_DEVICE_TABLE(x86cpu, pcmul_cpu_id); > + > +static int __init polyval_clmulni_mod_init(void) > +{ > + if (!x86_match_cpu(pcmul_cpu_id)) > + return -ENODEV; > + > + return crypto_register_shash(&polyval_alg); > +} > + > +static void __exit polyval_clmulni_mod_exit(void) > +{ > + crypto_unregister_shash(&polyval_alg); > +} This won't work as intended; it's registering the algorithm (and autoloading the module) if PCLMUL *or* AVX is available, rather than PCLMUL *and* AVX. I think the way to go is to just have X86_FEATURE_PCLMULQDQ in the table, like before, and add a check for boot_cpu_has(X86_FEATURE_AVX) in the init function. - Eric