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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR12MB2759.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 41f95eb8-cd41-4576-a80d-08da547b75f4 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Jun 2022 18:17:26.2712 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: WrR6E3E/AZMm4zuuIansM/+egg1HBomf2Iu9lrblVKtScFvkxVNB3cGxxeSggfiLcCMUqOyO922dhtLReOWdxw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4334 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org [AMD Official Use Only - General] >>> /* >>> * The RMP entry format is not architectural. The format is defined=20 >>> in PPR @@ -126,6 +128,15 @@ struct snp_guest_platform_data { >>> u64 secrets_gpa; >>> }; >>> =20 >>> +struct rmpupdate { >>> + u64 gpa; >>> + u8 assigned; >>> + u8 pagesize; >>> + u8 immutable; >>> + u8 rsvd; >>> + u32 asid; >>> +} __packed; >>I see above it says the RMP entry format isn't architectural; is this 'rm= pupdate' structure? If not how is this going to get handled when we have a = couple >of SNP capable CPUs with different layouts? >Architectural implies that it is defined in the APM and shouldn't change i= n such a way as to not be backward compatible.=20 >I probably think the wording here should be architecture independent or mo= re precisely platform independent. Some more clarity on this:=20 Actually, the PPR for family 19h Model 01h, Rev B1 defines the RMP entry fo= rmat as below: 2.1.4.2 RMP Entry Format Architecturally the format of RMP entries are not specified in APM. In orde= r to assist software, the following table specifies select portions of the = RMP entry format for this specific product. Each RMP entry is 16B in size a= nd is formatted as follows. Software should not rely on any field definitio= ns not specified in this table and the format of an RMP entry may change in= future processors.=20 Architectural implies that it is defined in the APM and shouldn't change in= such a way as to not be backward compatible. So non-architectural in this = context means that it is only defined in our PPR. So actually this RPM entry definition is platform dependent and will need t= o be changed for different AMD processors and that change has to be handled= correspondingly in the dump_rmpentry() code.=20 Thanks, Ashish