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Message-ID: <653f4dd9-1325-22f5-1fe0-79e0ec9d2283@arm.com>
Date:   Wed, 13 Jul 2022 15:52:10 +0100
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Subject: Re: [PATCH] random: vary jitter iterations based on cycle counter
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To:     "Jason A. Donenfeld" <Jason@zx2c4.com>
Cc:     linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org,
        Eric Biggers <ebiggers@google.com>,
        Theodore Ts'o <tytso@mit.edu>,
        Linus Torvalds <torvalds@linux-foundation.org>
References: <20220422132027.1267060-1-Jason@zx2c4.com>
 <eb74e1b8-af7e-21e8-658f-af6c7975264e@arm.com> <Ys7ZURKkoHw8Bp+q@zx2c4.com>
From:   Vladimir Murzin <vladimir.murzin@arm.com>
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Hi Jason,

On 7/13/22 15:40, Jason A. Donenfeld wrote:
> Hi Vladimir,
> 
> On Wed, Jul 13, 2022 at 03:31:05PM +0100, Vladimir Murzin wrote:
>> I've just seen on the platform with slow(ish) timer that it is now considered
>> as a source of entropy with samples_per_bit set to 27 (5.19-rc6 has MAX_SAMPLES_PER_BIT
>> set to 32). Because of that I see significant delays and I'm trying to understand what
>> could be wrong with my setup.
>>
>> I observe one credit_init_bits(1) call (via entropy_timer()) per ~970 schedule() calls.
>> Is that somewhat expected? Does it make sense at all?
> 
> How slow are we talking? Seconds? Minutes? Is it too slow? It's possible
> that MAX_SAMPLES_PER_BIT=32 is a bit high as a threshold and I should
> reduce that a bit.
> 

TBH, I run out of patience and never seen it completes, more then seconds. I just was
curious how much it is should take to get crng_ready() return true.

> Also, out of curiosity, why is your timer so slow?

It is part of slow(ish) FPGA.

Cheers
Vladimir

> 
> Jason