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From:   Tomer Maimon <tmaimon77@gmail.com>
To:     <avifishman70@gmail.com>, <tali.perry1@gmail.com>,
        <joel@jms.id.au>, <venture@google.com>, <yuenn@google.com>,
        <benjaminfair@google.com>, <olivia@selenic.com>,
        <herbert@gondor.apana.org.au>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>
CC:     <openbmc@lists.ozlabs.org>, <linux-crypto@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
        Tomer Maimon <tmaimon77@gmail.com>
Subject: [PATCH v1 2/2] hwrng: npcm: Add NPCM8XX support
Date:   Thu, 22 Sep 2022 17:22:16 +0300
Message-ID: <20220922142216.17581-3-tmaimon77@gmail.com>
In-Reply-To: <20220922142216.17581-1-tmaimon77@gmail.com>
References: <20220922142216.17581-1-tmaimon77@gmail.com>
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Adding RNG NPCM8XX support to NPCM RNG driver.
RNG NPCM8XX uses a different clock prescaler.

As part of adding NPCM8XX support:
- Add NPCM8XX specific compatible string.
- Add NPCM8XX specific clock prescaler.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 drivers/char/hw_random/npcm-rng.c | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/char/hw_random/npcm-rng.c b/drivers/char/hw_random/npcm-rng.c
index 1ec5f267a656..705be9ccae31 100644
--- a/drivers/char/hw_random/npcm-rng.c
+++ b/drivers/char/hw_random/npcm-rng.c
@@ -18,10 +18,11 @@
 #define NPCM_RNGD_REG		0x04	/* Data register */
 #define NPCM_RNGMODE_REG	0x08	/* Mode register */
 
-#define NPCM_RNG_CLK_SET_25MHZ	GENMASK(4, 3) /* 20-25 MHz */
-#define NPCM_RNG_DATA_VALID	BIT(1)
-#define NPCM_RNG_ENABLE		BIT(0)
-#define NPCM_RNG_M1ROSEL	BIT(1)
+#define NPCM_RNG_CLK_SET_25MHZ		GENMASK(4, 3) /* 20-25 MHz */
+#define NPCM_RNG_CLK_SET_62_5MHZ	BIT(2) /* 60-80 MHz */
+#define NPCM_RNG_DATA_VALID		BIT(1)
+#define NPCM_RNG_ENABLE			BIT(0)
+#define NPCM_RNG_M1ROSEL		BIT(1)
 
 #define NPCM_RNG_TIMEOUT_USEC	20000
 #define NPCM_RNG_POLL_USEC	1000
@@ -31,14 +32,14 @@
 struct npcm_rng {
 	void __iomem *base;
 	struct hwrng rng;
+	u32 clkp;
 };
 
 static int npcm_rng_init(struct hwrng *rng)
 {
 	struct npcm_rng *priv = to_npcm_rng(rng);
 
-	writel(NPCM_RNG_CLK_SET_25MHZ | NPCM_RNG_ENABLE,
-	       priv->base + NPCM_RNGCS_REG);
+	writel(priv->clkp | NPCM_RNG_ENABLE, priv->base + NPCM_RNGCS_REG);
 
 	return 0;
 }
@@ -47,7 +48,7 @@ static void npcm_rng_cleanup(struct hwrng *rng)
 {
 	struct npcm_rng *priv = to_npcm_rng(rng);
 
-	writel(NPCM_RNG_CLK_SET_25MHZ, priv->base + NPCM_RNGCS_REG);
+	writel(priv->clkp, priv->base + NPCM_RNGCS_REG);
 }
 
 static int npcm_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
@@ -102,6 +103,11 @@ static int npcm_rng_probe(struct platform_device *pdev)
 	pm_runtime_use_autosuspend(&pdev->dev);
 	pm_runtime_enable(&pdev->dev);
 
+	if (of_device_is_compatible(pdev->dev.of_node, "nuvoton,npcm750-rng"))
+		priv->clkp = NPCM_RNG_CLK_SET_25MHZ;
+	if (of_device_is_compatible(pdev->dev.of_node, "nuvoton,npcm845-rng"))
+		priv->clkp = NPCM_RNG_CLK_SET_62_5MHZ;
+
 #ifndef CONFIG_PM
 	priv->rng.init = npcm_rng_init;
 	priv->rng.cleanup = npcm_rng_cleanup;
@@ -163,6 +169,7 @@ static const struct dev_pm_ops npcm_rng_pm_ops = {
 
 static const struct of_device_id rng_dt_id[] __maybe_unused = {
 	{ .compatible = "nuvoton,npcm750-rng",  },
+	{ .compatible = "nuvoton,npcm845-rng",  },
 	{},
 };
 MODULE_DEVICE_TABLE(of, rng_dt_id);
-- 
2.33.0