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Date:   Mon, 9 Jan 2023 18:02:28 +0000
From:   Conor Dooley <conor@kernel.org>
To:     Jia Jie Ho <jiajie.ho@starfivetech.com>
Cc:     Olivia Mackall <olivia@selenic.com>,
        Herbert Xu <herbert@gondor.apana.org.au>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Emil Renner Berthing <kernel@esmil.dk>,
        Conor Dooley <conor.dooley@microchip.com>,
        linux-crypto@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [PATCH v3 3/3] riscv: dts: starfive: Add TRNG node for
 VisionFive 2
Message-ID: <Y7xWtFZO/Y7GaYRQ@spud>
References: <20230109165249.110279-1-jiajie.ho@starfivetech.com>
 <20230109165249.110279-4-jiajie.ho@starfivetech.com>
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Hey folks,

On Tue, Jan 10, 2023 at 12:52:49AM +0800, Jia Jie Ho wrote:
> Adding StarFive TRNG controller node to VisionFive 2 SoC.
>=20
> Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com>
> Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com>
> Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
> ---
>  arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>=20
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/d=
ts/starfive/jh7110.dtsi
> index 4ac159d79d66..3c29e0bc6246 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -455,5 +455,15 @@ uart5: serial@12020000 {
>  			reg-shift =3D <2>;
>  			status =3D "disabled";
>  		};
> +
> +		rng: rng@1600c000 {
> +			compatible =3D "starfive,jh7110-trng";
> +			reg =3D <0x0 0x1600C000 0x0 0x4000>;
> +			clocks =3D <&stgcrg JH7110_STGCLK_SEC_HCLK>,
> +				 <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;

Which clock source is this? I see syscrg and aoncrg in the v3
devicetree:
https://lore.kernel.org/linux-riscv/20221220011247.35560-7-hal.feng@starfiv=
etech.com/

Have a missed a patchset which adds support for this particular clock
controller? At the very least, I don't think one has reached the
linux-riscv mailing list.
The clock driver patchset only has aoncrg & syscrg:
https://lore.kernel.org/linux-riscv/20221220005054.34518-1-hal.feng@starfiv=
etech.com/


> +			clock-names =3D "hclk", "ahb";
> +			resets =3D <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
> +			interrupts =3D <30>;
> +		};
>  	};
>  };

Thanks,
Conor.


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