Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E78CC636D6 for ; Thu, 2 Feb 2023 13:50:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231575AbjBBNuq (ORCPT ); Thu, 2 Feb 2023 08:50:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46090 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231339AbjBBNuq (ORCPT ); Thu, 2 Feb 2023 08:50:46 -0500 Received: from mail-ed1-x542.google.com (mail-ed1-x542.google.com [IPv6:2a00:1450:4864:20::542]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EAC7174A57 for ; Thu, 2 Feb 2023 05:50:43 -0800 (PST) Received: by mail-ed1-x542.google.com with SMTP id z11so2077418ede.1 for ; Thu, 02 Feb 2023 05:50:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Rf0VgEByS+dEGqCN3splXKV9KTkduOfaE2qRRkUgcps=; b=OR0NdpgRzgqiIthozDCVRgHAC3fFyIBoH0kh6aoDCmRIX0KTCVhFyFtPgiB9/s3uns bgiMqn9XVJc67Iq+Y8S4LupNgVowFXCotbmCLTKdp5RNg+2CXUeXuBxWIfNLz10LHaua 3wjDND9W2uYeAv6/2A3MwH9tt8D58nT9w+j/vGSFF6mDBRcWX/8aWb2BDuIstaBjcFp9 BviKgZiH5a7tjQu07J172vq/MUPhU95ywunNvSpf9fGz2q4VcNEWEO6OJtQS9Sx/W3Uh kjrexaPgBDfSlB5OTlNGkWDpcq7H/Ig92zZA3A4UhdobdsWNyMyb3YvR0LWezoKM8NOQ 1BWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Rf0VgEByS+dEGqCN3splXKV9KTkduOfaE2qRRkUgcps=; b=wtXuEEQfpRvM19eT9OnFuejUHk/lUoXpGYfhssCOLTFA2qduSmrVpW1rn2JRCDkzTH skCqY1OFRID9X9pd9ZoiVaORG5kAJpTB78rHxkLuwuyPKl6w0dwUCO7shV6V2pA7veyO 4wCDXM43Ju2SM6SzjuLBilvq15DRW/9CDwaRvVxJEvobKAMihk8BfWy4c62nDv36asmB zTKUMRS1wjnLwNpFtb5nAPE5KiQWJppbi77p0lT1JaAfEiVTqdVxgARuXMcMt3iog+FW eKW9HDRQMeiQpg+u94BgPI81ErN3VaBNILq1BsII0i/E3SNGYGtCt8HBtKP/AX/dUGQh qstA== X-Gm-Message-State: AO0yUKWRsFVziKgr602An8v9ZE7Qt8j3RHnosBMfmpxr4z5fU1Na3I9f QcMGLX8qILg4RsITf4cdcFGp5A== X-Google-Smtp-Source: AK7set/DOJzZLgThxp0kv0e2P5JlVxnl3aQz6FJjGZ81Z2x9kfnHTdGMW3kx2Icjs5DTswJdsRh2xw== X-Received: by 2002:a05:6402:74c:b0:4a2:590b:668a with SMTP id p12-20020a056402074c00b004a2590b668amr6527959edy.3.1675345842515; Thu, 02 Feb 2023 05:50:42 -0800 (PST) Received: from localhost.localdomain (88-112-131-206.elisa-laajakaista.fi. [88.112.131.206]) by smtp.gmail.com with ESMTPSA id r23-20020aa7c157000000b0049e1f167956sm7596332edp.9.2023.02.02.05.50.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Feb 2023 05:50:42 -0800 (PST) From: Vladimir Zapolskiy To: Krzysztof Kozlowski , Bjorn Andersson , Herbert Xu , Thara Gopinath , Bhupesh Sharma Cc: Rob Herring , Konrad Dybcio , Andy Gross , "David S. Miller" , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, Rob Herring , Jordan Crouse Subject: [PATCH v8 1/9] dt-bindings: qcom-qce: Convert bindings to yaml Date: Thu, 2 Feb 2023 15:50:28 +0200 Message-Id: <20230202135036.2635376-2-vladimir.zapolskiy@linaro.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20230202135036.2635376-1-vladimir.zapolskiy@linaro.org> References: <20230202135036.2635376-1-vladimir.zapolskiy@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Bhupesh Sharma Convert Qualcomm QCE crypto devicetree binding to YAML. Reviewed-by: Rob Herring Reviewed-by: Bjorn Andersson Tested-by: Jordan Crouse Signed-off-by: Bhupesh Sharma Signed-off-by: Vladimir Zapolskiy --- .../devicetree/bindings/crypto/qcom-qce.txt | 25 ------- .../devicetree/bindings/crypto/qcom-qce.yaml | 67 +++++++++++++++++++ 2 files changed, 67 insertions(+), 25 deletions(-) delete mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.txt create mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.yaml diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.txt b/Documentation/devicetree/bindings/crypto/qcom-qce.txt deleted file mode 100644 index fdd53b184ba8..000000000000 --- a/Documentation/devicetree/bindings/crypto/qcom-qce.txt +++ /dev/null @@ -1,25 +0,0 @@ -Qualcomm crypto engine driver - -Required properties: - -- compatible : should be "qcom,crypto-v5.1" -- reg : specifies base physical address and size of the registers map -- clocks : phandle to clock-controller plus clock-specifier pair -- clock-names : "iface" clocks register interface - "bus" clocks data transfer interface - "core" clocks rest of the crypto block -- dmas : DMA specifiers for tx and rx dma channels. For more see - Documentation/devicetree/bindings/dma/dma.txt -- dma-names : DMA request names should be "rx" and "tx" - -Example: - crypto@fd45a000 { - compatible = "qcom,crypto-v5.1"; - reg = <0xfd45a000 0x6000>; - clocks = <&gcc GCC_CE2_AHB_CLK>, - <&gcc GCC_CE2_AXI_CLK>, - <&gcc GCC_CE2_CLK>; - clock-names = "iface", "bus", "core"; - dmas = <&cryptobam 2>, <&cryptobam 3>; - dma-names = "rx", "tx"; - }; diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml new file mode 100644 index 000000000000..8df47e8513b8 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm crypto engine driver + +maintainers: + - Bhupesh Sharma + +description: + This document defines the binding for the QCE crypto + controller found on Qualcomm parts. + +properties: + compatible: + const: qcom,crypto-v5.1 + + reg: + maxItems: 1 + + clocks: + items: + - description: iface clocks register interface. + - description: bus clocks data transfer interface. + - description: core clocks rest of the crypto block. + + clock-names: + items: + - const: iface + - const: bus + - const: core + + dmas: + items: + - description: DMA specifiers for rx dma channel. + - description: DMA specifiers for tx dma channel. + + dma-names: + items: + - const: rx + - const: tx + +required: + - compatible + - reg + - clocks + - clock-names + - dmas + - dma-names + +additionalProperties: false + +examples: + - | + #include + crypto-engine@fd45a000 { + compatible = "qcom,crypto-v5.1"; + reg = <0xfd45a000 0x6000>; + clocks = <&gcc GCC_CE2_AHB_CLK>, + <&gcc GCC_CE2_AXI_CLK>, + <&gcc GCC_CE2_CLK>; + clock-names = "iface", "bus", "core"; + dmas = <&cryptobam 2>, <&cryptobam 3>; + dma-names = "rx", "tx"; + }; -- 2.33.0