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([2401:4900:1c5f:7a7d:9c44:b2ee:ae34:5374]) by smtp.gmail.com with ESMTPSA id e22-20020aa78256000000b00592626fe48csm1278584pfn.122.2023.02.09.04.21.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 09 Feb 2023 04:21:24 -0800 (PST) Message-ID: <7b38331c-3b29-03c1-fbed-f5799d11ca1f@linaro.org> Date: Thu, 9 Feb 2023 17:51:19 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.1 Subject: Re: [PATCH v9 11/14] arm64: dts: qcom: sm8250: add description of Qualcomm Crypto Engine IP To: Vladimir Zapolskiy , Krzysztof Kozlowski , Bjorn Andersson , Herbert Xu , Thara Gopinath Cc: Rob Herring , Konrad Dybcio , Andy Gross , "David S. Miller" , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org References: <20230208183755.2907771-1-vladimir.zapolskiy@linaro.org> <20230208183755.2907771-12-vladimir.zapolskiy@linaro.org> Content-Language: en-US From: Bhupesh Sharma In-Reply-To: <20230208183755.2907771-12-vladimir.zapolskiy@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Hi Vladimir, On 2/9/23 12:07 AM, Vladimir Zapolskiy wrote: > Add description of QCE and its corresponding BAM DMA IPs on SM8250 SoC. > > Signed-off-by: Vladimir Zapolskiy > --- > arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi > index e59c16f74d17..d8698d18223e 100644 > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi > @@ -2215,6 +2215,30 @@ ufs_mem_phy_lanes: phy@1d87400 { > }; > }; > > + cryptobam: dma-controller@1dc4000 { > + compatible = "qcom,bam-v1.7.0"; > + reg = <0x0 0x01dc4000 0x0 0x24000>; > + interrupts = ; > + #dma-cells = <1>; > + qcom,ee = <0>; > + qcom,controlled-remotely; > + num-channels = <8>; > + qcom,num-ees = <2>; > + iommus = <&apps_smmu 0x586 0x11>, > + <&apps_smmu 0x596 0x11>; > + }; > + > + crypto: crypto@1dfa000 { > + compatible = "qcom,sm8250-qce", "qcom,sm8150-qce"; > + reg = <0x0 0x01dfa000 0x0 0x6000>; > + dmas = <&cryptobam 6>, <&cryptobam 7>; > + dma-names = "rx", "tx"; > + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 &mc_virt SLAVE_EBI_CH0>; > + interconnect-names = "memory"; > + iommus = <&apps_smmu 0x586 0x11>, > + <&apps_smmu 0x596 0x11>; > + }; > + > tcsr_mutex: hwlock@1f40000 { > compatible = "qcom,tcsr-mutex"; > reg = <0x0 0x01f40000 0x0 0x40000>; This patch was part of the v7 arm64 dts fixes I sent out - see [1]. Probably you can use it as a base and make the changes (interconnect property for the BAM DMA node and qce-compatible names) directly there and include it in your patch series. [1]. https://lore.kernel.org/linux-arm-msm/20220921045602.1462007-3-bhupesh.sharma@linaro.org/ Thanks, Bhupesh