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Subject: Re: [PATCH] x86: enable Data Operand Independent Timing Mode
From:   Roxana Bradescu <roxabee@chromium.org>
In-Reply-To: <fbf8d93e-2426-67f7-33c6-fe7d1a1a15b2@intel.com>
Date:   Thu, 2 Mar 2023 19:32:41 -0800
Cc:     Eric Biggers <ebiggers@kernel.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
        Dave Hansen <dave.hansen@linux.intel.com>,
        "H . Peter Anvin" <hpa@zytor.com>, x86@kernel.org,
        linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-hardening@vger.kernel.org,
        Peter Zijlstra <peterz@infradead.org>,
        Adam Langley <agl@google.com>,
        Ard Biesheuvel <ardb@kernel.org>,
        "Jason A . Donenfeld" <Jason@zx2c4.com>,
        Pawan Kumar Gupta <pawan.kumar.gupta@intel.com>,
        Daniel Sneddon <daniel.sneddon@linux.intel.com>
Message-Id: <29D41476-1617-4F6C-9046-82FBE70E01C9@chromium.org>
References: <20230125012801.362496-1-ebiggers@kernel.org>
 <fbf8d93e-2426-67f7-33c6-fe7d1a1a15b2@intel.com>
To:     Dave Hansen <dave.hansen@intel.com>
Precedence: bulk


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> On Feb 3, 2023, at 10:25 AM, Dave Hansen <dave.hansen@intel.com> =
wrote:
>=20
> BTW, I'm basically moving forward assuming that we're going to apply
> this patch in _some_ form.  I'm going to make some changes, but I'll
> discuss them in this thread to make sure we're all on the same page =
first.

Just checking in on the changes mentioned here.

> On 1/24/23 17:28, Eric Biggers wrote:
>> +Affected CPUs
>> +-------------
>> +
>> +This vulnerability affects Intel Core family processors based on the =
Ice Lake
>> +and later microarchitectures, and Intel Atom family processors based =
on the
>> +Gracemont and later microarchitectures.  For more information, see =
Intel's
>> +documentation [1]_.
>=20
> I had a hard time following the docs in this area.
>=20
> But I'm not sure this statement is correct.  The docs actually say:
>=20
> 	For Intel=C2=AE Core=E2=84=A2 family processors based on =
microarchitectures
> 	before Ice Lake and Intel Atom=C2=AE family processors based on
> 	microarchitectures before Gracemont that do not enumerate
> 	IA32_UARCH_MISC_CTL, developers may assume that the instructions
> 	listed here operate as if DOITM is enabled.

Have we been able to clarify if this assumption is guaranteed?

>=20
> A processor needs to be before "Ice Lake" and friends *AND* not
> enumerate IA32_UARCH_MISC_CTL to be unaffected.
>=20
> There's also another tweak that's needed because:
>=20
> 	Processors that do not enumerate IA32_ARCH_CAPABILITIES[DOITM]
> 	when the latest microcode is applied do not need to set
> 	IA32_UARCH_MISC_CTL [DOITM] in order to have the behavior
> 	described in this document...
>=20
> First, we need to mention the "latest microcode" thing in the kernel
> docs.  I also _think_ the whole "microarchitectures before" stuff is
> rather irrelevant and we can simplify this down to:
>=20
> 	This vulnerability affects all Intel processors that support
> 	MSR_IA32_ARCH_CAPABILITIES and set =
MSR_IA32_ARCH_CAPABILITIES[DOITM]
> 	when the latest microcode is applied.
>=20

Certainly a lot cleaner. Would be great if the Intel docs reflected =
this.

=E2=80=94
Regards, Roxana


> Which reminds me.  This:
>=20
>> +void update_doitm_msr(void)
>> +{
>> +	u64 msr;
>> +
>> +	if (doitm_off)
>> +		return;
>> +
>> +	rdmsrl(MSR_IA32_UARCH_MISC_CTL, msr);
>> +	wrmsrl(MSR_IA32_UARCH_MISC_CTL, msr | UARCH_MISC_DOITM);
>> +}
>=20
> should probably be:
>=20
> void update_doitm_msr(void)
> {
> 	u64 msr;
>=20
> 	/*
> 	 * All processors that enumerate support for DOIT
> 	 * are affected *and* have the mitigation available.
> 	 */
> 	if (!boot_cpu_has_bug(X86_BUG_DODT))
> 		return;
>=20
> 	rdmsrl(MSR_IA32_UARCH_MISC_CTL, msr);
> 	if (doitm_off)
> 		msr &=3D ~UARCH_MISC_DOITM;
> 	else
> 		msr |=3D UARCH_MISC_DOITM;
> 	wrmsrl(MSR_IA32_UARCH_MISC_CTL, msr);
> }
>=20
> in case the CPU isn't actually coming out of reset, like if kexec() =
left
> DOITM=3D1.
>=20


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