From:   Varun Sethi <V.Sethi@nxp.com>
To:     Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>,
        Horia Geanta <horia.geanta@nxp.com>,
        Pankaj Gupta <pankaj.gupta@nxp.com>,
        Gaurav Jain <gaurav.jain@nxp.com>,
        "herbert@gondor.apana.org.au" <herbert@gondor.apana.org.au>,
        "davem@davemloft.net" <davem@davemloft.net>,
        "linux-crypto@vger.kernel.org" <linux-crypto@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH 1/2] crypto: caam - reduce page 0 regs access to minimum
Thread-Topic: [PATCH 1/2] crypto: caam - reduce page 0 regs access to minimum
Thread-Index: AQHZTM84TTjIbnfyN0mJ/yPRPLdXRq8DfoxQ
Date:   Mon, 20 Mar 2023 09:12:49 +0000
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References: <20230302062055.1564514-1-meenakshi.aggarwal@nxp.com>
 <20230302062055.1564514-2-meenakshi.aggarwal@nxp.com>
In-Reply-To: <20230302062055.1564514-2-meenakshi.aggarwal@nxp.com>
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Reviewed-by: Varun Sethi <v.sethi@nxp.com>


Regards
Varun

> -----Original Message-----
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> Sent: Thursday, March 2, 2023 11:51 AM
> To: Horia Geanta <horia.geanta@nxp.com>; Varun Sethi <V.Sethi@nxp.com>;
> Pankaj Gupta <pankaj.gupta@nxp.com>; Gaurav Jain <gaurav.jain@nxp.com>;
> herbert@gondor.apana.org.au; davem@davemloft.net; linux-
> crypto@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: [PATCH 1/2] crypto: caam - reduce page 0 regs access to minimum
>=20
> From: Horia GeantA <horia.geanta@nxp.com>
>=20
> Use job ring register map, in place of controller register map to access =
page 0
> registers, as access to the controller register map is not permitted.
>=20
> Signed-off-by: Horia GeantA <horia.geanta@nxp.com>
> ---
>  drivers/crypto/caam/caamalg.c  | 21 +++++-----
> drivers/crypto/caam/caamhash.c | 10 +++--  drivers/crypto/caam/caampkc.c =
 |
> 6 +--  drivers/crypto/caam/caamrng.c  |  6 +--
>  drivers/crypto/caam/ctrl.c     | 74 +++++++++++++++++++++-------------
>  drivers/crypto/caam/debugfs.c  |  8 ++--  drivers/crypto/caam/debugfs.h =
 |  7
> +++-
>  7 files changed, 78 insertions(+), 54 deletions(-)
>=20
> diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.=
c
> index 4a9b998a8d26..29838b80a0bb 100644
> --- a/drivers/crypto/caam/caamalg.c
> +++ b/drivers/crypto/caam/caamalg.c
> @@ -3,7 +3,7 @@
>   * caam - Freescale FSL CAAM support for crypto API
>   *
>   * Copyright 2008-2011 Freescale Semiconductor, Inc.
> - * Copyright 2016-2019 NXP
> + * Copyright 2016-2019, 2023 NXP
>   *
>   * Based on talitos crypto API driver.
>   *
> @@ -3530,13 +3530,14 @@ int caam_algapi_init(struct device *ctrldev)
>  	 * First, detect presence and attributes of DES, AES, and MD blocks.
>  	 */
>  	if (priv->era < 10) {
> +		struct caam_perfmon __iomem *perfmon =3D &priv->jr[0]-
> >perfmon;
>  		u32 cha_vid, cha_inst, aes_rn;
>=20
> -		cha_vid =3D rd_reg32(&priv->ctrl->perfmon.cha_id_ls);
> +		cha_vid =3D rd_reg32(&perfmon->cha_id_ls);
>  		aes_vid =3D cha_vid & CHA_ID_LS_AES_MASK;
>  		md_vid =3D (cha_vid & CHA_ID_LS_MD_MASK) >>
> CHA_ID_LS_MD_SHIFT;
>=20
> -		cha_inst =3D rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
> +		cha_inst =3D rd_reg32(&perfmon->cha_num_ls);
>  		des_inst =3D (cha_inst & CHA_ID_LS_DES_MASK) >>
>  			   CHA_ID_LS_DES_SHIFT;
>  		aes_inst =3D cha_inst & CHA_ID_LS_AES_MASK; @@ -3544,23
> +3545,23 @@ int caam_algapi_init(struct device *ctrldev)
>  		ccha_inst =3D 0;
>  		ptha_inst =3D 0;
>=20
> -		aes_rn =3D rd_reg32(&priv->ctrl->perfmon.cha_rev_ls) &
> -			 CHA_ID_LS_AES_MASK;
> +		aes_rn =3D rd_reg32(&perfmon->cha_rev_ls) &
> CHA_ID_LS_AES_MASK;
>  		gcm_support =3D !(aes_vid =3D=3D CHA_VER_VID_AES_LP && aes_rn <
> 8);
>  	} else {
> +		struct version_regs __iomem *vreg =3D &priv->jr[0]->vreg;
>  		u32 aesa, mdha;
>=20
> -		aesa =3D rd_reg32(&priv->ctrl->vreg.aesa);
> -		mdha =3D rd_reg32(&priv->ctrl->vreg.mdha);
> +		aesa =3D rd_reg32(&vreg->aesa);
> +		mdha =3D rd_reg32(&vreg->mdha);
>=20
>  		aes_vid =3D (aesa & CHA_VER_VID_MASK) >>
> CHA_VER_VID_SHIFT;
>  		md_vid =3D (mdha & CHA_VER_VID_MASK) >>
> CHA_VER_VID_SHIFT;
>=20
> -		des_inst =3D rd_reg32(&priv->ctrl->vreg.desa) &
> CHA_VER_NUM_MASK;
> +		des_inst =3D rd_reg32(&vreg->desa) & CHA_VER_NUM_MASK;
>  		aes_inst =3D aesa & CHA_VER_NUM_MASK;
>  		md_inst =3D mdha & CHA_VER_NUM_MASK;
> -		ccha_inst =3D rd_reg32(&priv->ctrl->vreg.ccha) &
> CHA_VER_NUM_MASK;
> -		ptha_inst =3D rd_reg32(&priv->ctrl->vreg.ptha) &
> CHA_VER_NUM_MASK;
> +		ccha_inst =3D rd_reg32(&vreg->ccha) & CHA_VER_NUM_MASK;
> +		ptha_inst =3D rd_reg32(&vreg->ptha) & CHA_VER_NUM_MASK;
>=20
>  		gcm_support =3D aesa & CHA_VER_MISC_AES_GCM;
>  	}
> diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhas=
h.c
> index 82d3c730a502..80deb003f0a5 100644
> --- a/drivers/crypto/caam/caamhash.c
> +++ b/drivers/crypto/caam/caamhash.c
> @@ -3,7 +3,7 @@
>   * caam - Freescale FSL CAAM support for ahash functions of crypto API
>   *
>   * Copyright 2011 Freescale Semiconductor, Inc.
> - * Copyright 2018-2019 NXP
> + * Copyright 2018-2019, 2023 NXP
>   *
>   * Based on caamalg.c crypto API driver.
>   *
> @@ -1956,12 +1956,14 @@ int caam_algapi_hash_init(struct device *ctrldev)
>  	 * presence and attributes of MD block.
>  	 */
>  	if (priv->era < 10) {
> -		md_vid =3D (rd_reg32(&priv->ctrl->perfmon.cha_id_ls) &
> +		struct caam_perfmon __iomem *perfmon =3D &priv->jr[0]-
> >perfmon;
> +
> +		md_vid =3D (rd_reg32(&perfmon->cha_id_ls) &
>  			  CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
> -		md_inst =3D (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) &
> +		md_inst =3D (rd_reg32(&perfmon->cha_num_ls) &
>  			   CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
>  	} else {
> -		u32 mdha =3D rd_reg32(&priv->ctrl->vreg.mdha);
> +		u32 mdha =3D rd_reg32(&priv->jr[0]->vreg.mdha);
>=20
>  		md_vid =3D (mdha & CHA_VER_VID_MASK) >>
> CHA_VER_VID_SHIFT;
>  		md_inst =3D mdha & CHA_VER_NUM_MASK;
> diff --git a/drivers/crypto/caam/caampkc.c b/drivers/crypto/caam/caampkc.=
c
> index e40614fef39d..72afc249d42f 100644
> --- a/drivers/crypto/caam/caampkc.c
> +++ b/drivers/crypto/caam/caampkc.c
> @@ -3,7 +3,7 @@
>   * caam - Freescale FSL CAAM support for Public Key Cryptography
>   *
>   * Copyright 2016 Freescale Semiconductor, Inc.
> - * Copyright 2018-2019 NXP
> + * Copyright 2018-2019, 2023 NXP
>   *
>   * There is no Shared Descriptor for PKC so that the Job Descriptor must=
 carry
>   * all the desired key parameters, input and output pointers.
> @@ -1168,10 +1168,10 @@ int caam_pkc_init(struct device *ctrldev)
>=20
>  	/* Determine public key hardware accelerator presence. */
>  	if (priv->era < 10) {
> -		pk_inst =3D (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) &
> +		pk_inst =3D (rd_reg32(&priv->jr[0]->perfmon.cha_num_ls) &
>  			   CHA_ID_LS_PK_MASK) >> CHA_ID_LS_PK_SHIFT;
>  	} else {
> -		pkha =3D rd_reg32(&priv->ctrl->vreg.pkha);
> +		pkha =3D rd_reg32(&priv->jr[0]->vreg.pkha);
>  		pk_inst =3D pkha & CHA_VER_NUM_MASK;
>=20
>  		/*
> diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.=
c
> index 1fd8ff965006..50eb55da45c2 100644
> --- a/drivers/crypto/caam/caamrng.c
> +++ b/drivers/crypto/caam/caamrng.c
> @@ -3,7 +3,7 @@
>   * caam - Freescale FSL CAAM support for hw_random
>   *
>   * Copyright 2011 Freescale Semiconductor, Inc.
> - * Copyright 2018-2019 NXP
> + * Copyright 2018-2019, 2023 NXP
>   *
>   * Based on caamalg.c crypto API driver.
>   *
> @@ -227,10 +227,10 @@ int caam_rng_init(struct device *ctrldev)
>=20
>  	/* Check for an instantiated RNG before registration */
>  	if (priv->era < 10)
> -		rng_inst =3D (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) &
> +		rng_inst =3D (rd_reg32(&priv->jr[0]->perfmon.cha_num_ls) &
>  			    CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
>  	else
> -		rng_inst =3D rd_reg32(&priv->ctrl->vreg.rng) &
> CHA_VER_NUM_MASK;
> +		rng_inst =3D rd_reg32(&priv->jr[0]->vreg.rng) &
> CHA_VER_NUM_MASK;
>=20
>  	if (!rng_inst)
>  		return 0;
> diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c inde=
x
> 6278afb951c3..be9724d05d01 100644
> --- a/drivers/crypto/caam/ctrl.c
> +++ b/drivers/crypto/caam/ctrl.c
> @@ -3,7 +3,7 @@
>   * Controller-level driver, kernel property detection, initialization
>   *
>   * Copyright 2008-2012 Freescale Semiconductor, Inc.
> - * Copyright 2018-2019 NXP
> + * Copyright 2018-2019, 2023 NXP
>   */
>=20
>  #include <linux/device.h>
> @@ -395,7 +395,7 @@ static void kick_trng(struct platform_device *pdev, i=
nt
> ent_delay)
>  		      RTMCTL_SAMP_MODE_RAW_ES_SC);
>  }
>=20
> -static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl)
> +static int caam_get_era_from_hw(struct caam_perfmon __iomem *perfmon)
>  {
>  	static const struct {
>  		u16 ip_id;
> @@ -421,12 +421,12 @@ static int caam_get_era_from_hw(struct caam_ctrl
> __iomem *ctrl)
>  	u16 ip_id;
>  	int i;
>=20
> -	ccbvid =3D rd_reg32(&ctrl->perfmon.ccb_id);
> +	ccbvid =3D rd_reg32(&perfmon->ccb_id);
>  	era =3D (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT;
>  	if (era)	/* This is '0' prior to CAAM ERA-6 */
>  		return era;
>=20
> -	id_ms =3D rd_reg32(&ctrl->perfmon.caam_id_ms);
> +	id_ms =3D rd_reg32(&perfmon->caam_id_ms);
>  	ip_id =3D (id_ms & SECVID_MS_IPID_MASK) >> SECVID_MS_IPID_SHIFT;
>  	maj_rev =3D (id_ms & SECVID_MS_MAJ_REV_MASK) >>
> SECVID_MS_MAJ_REV_SHIFT;
>=20
> @@ -446,7 +446,7 @@ static int caam_get_era_from_hw(struct caam_ctrl
> __iomem *ctrl)
>   *
>   * @ctrl:	controller region
>   */
> -static int caam_get_era(struct caam_ctrl __iomem *ctrl)
> +static int caam_get_era(struct caam_perfmon __iomem *perfmon)
>  {
>  	struct device_node *caam_node;
>  	int ret;
> @@ -459,7 +459,7 @@ static int caam_get_era(struct caam_ctrl __iomem *ctr=
l)
>  	if (!ret)
>  		return prop;
>  	else
> -		return caam_get_era_from_hw(ctrl);
> +		return caam_get_era_from_hw(perfmon);
>  }
>=20
>  /*
> @@ -626,6 +626,7 @@ static int caam_probe(struct platform_device *pdev)
>  	struct device_node *nprop, *np;
>  	struct caam_ctrl __iomem *ctrl;
>  	struct caam_drv_private *ctrlpriv;
> +	struct caam_perfmon __iomem *perfmon;
>  	struct dentry *dfs_root;
>  	u32 scfgr, comp_params;
>  	u8 rng_vid;
> @@ -665,9 +666,36 @@ static int caam_probe(struct platform_device *pdev)
>  		return ret;
>  	}
>=20
> -	caam_little_end =3D !(bool)(rd_reg32(&ctrl->perfmon.status) &
> +	ring =3D 0;
> +	for_each_available_child_of_node(nprop, np)
> +		if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
> +		    of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
> +			u32 reg;
> +
> +			if (of_property_read_u32_index(np, "reg", 0, &reg)) {
> +				dev_err(dev, "%s read reg property error\n",
> +					np->full_name);
> +				continue;
> +			}
> +
> +			ctrlpriv->jr[ring] =3D (struct caam_job_ring __iomem
> __force *)
> +					     ((__force uint8_t *)ctrl + reg);
> +
> +			ctrlpriv->total_jobrs++;
> +			ring++;
> +		}
> +
> +	/*
> +	 * Wherever possible, instead of accessing registers from the global
> page,
> +	 * use the alias registers in the first (cf. DT nodes order)
> +	 * job ring's page.
> +	 */
> +	perfmon =3D ring ? (struct caam_perfmon *)&ctrlpriv->jr[0]->perfmon :
> +			 (struct caam_perfmon *)&ctrl->perfmon;
> +
> +	caam_little_end =3D !(bool)(rd_reg32(&perfmon->status) &
>  				  (CSTA_PLEND | CSTA_ALT_PLEND));
> -	comp_params =3D rd_reg32(&ctrl->perfmon.comp_parms_ms);
> +	comp_params =3D rd_reg32(&perfmon->comp_parms_ms);
>  	if (comp_params & CTPR_MS_PS && rd_reg32(&ctrl->mcr) &
> MCFGR_LONG_PTR)
>  		caam_ptr_sz =3D sizeof(u64);
>  	else
> @@ -778,7 +806,7 @@ static int caam_probe(struct platform_device *pdev)
>  		return ret;
>  	}
>=20
> -	ctrlpriv->era =3D caam_get_era(ctrl);
> +	ctrlpriv->era =3D caam_get_era(perfmon);
>  	ctrlpriv->domain =3D iommu_get_domain_for_dev(dev);
>=20
>  	dfs_root =3D debugfs_create_dir(dev_name(dev), NULL); @@ -789,7
> +817,7 @@ static int caam_probe(struct platform_device *pdev)
>  			return ret;
>  	}
>=20
> -	caam_debugfs_init(ctrlpriv, dfs_root);
> +	caam_debugfs_init(ctrlpriv, perfmon, dfs_root);
>=20
>  	/* Check to see if (DPAA 1.x) QI present. If so, enable */
>  	if (ctrlpriv->qi_present && !caam_dpaa2) { @@ -808,19 +836,6 @@
> static int caam_probe(struct platform_device *pdev)  #endif
>  	}
>=20
> -	ring =3D 0;
> -	for_each_available_child_of_node(nprop, np)
> -		if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
> -		    of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
> -			ctrlpriv->jr[ring] =3D (struct caam_job_ring __iomem
> __force *)
> -					     ((__force uint8_t *)ctrl +
> -					     (ring + JR_BLOCK_NUMBER) *
> -					      BLOCK_OFFSET
> -					     );
> -			ctrlpriv->total_jobrs++;
> -			ring++;
> -		}
> -
>  	/* If no QI and no rings specified, quit and go home */
>  	if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
>  		dev_err(dev, "no queues configured, terminating\n"); @@ -
> 836,12 +851,17 @@ static int caam_probe(struct platform_device *pdev)
>  	 * check both here.
>  	 */
>  	if (ctrlpriv->era < 10) {
> -		rng_vid =3D (rd_reg32(&ctrl->perfmon.cha_id_ls) &
> +		rng_vid =3D (rd_reg32(&perfmon->cha_id_ls) &
>  			   CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
>  		ctrlpriv->blob_present =3D ctrlpriv->blob_present &&
>  			(rd_reg32(&ctrl->perfmon.cha_num_ls) &
> CHA_ID_LS_AES_MASK);
>  	} else {
> -		rng_vid =3D (rd_reg32(&ctrl->vreg.rng) & CHA_VER_VID_MASK) >>
> +		struct version_regs __iomem *vreg;
> +
> +		vreg =3D ring ? (struct version_regs *)&ctrlpriv->jr[0]->vreg :
> +			      (struct version_regs *)&ctrl->vreg;
> +
> +		rng_vid =3D (rd_reg32(&vreg->rng) & CHA_VER_VID_MASK) >>
>  			   CHA_VER_VID_SHIFT;
>  		ctrlpriv->blob_present =3D ctrlpriv->blob_present &&
>  			(rd_reg32(&ctrl->vreg.aesa) &
> CHA_VER_MISC_AES_NUM_MASK); @@ -925,8 +945,8 @@ static int
> caam_probe(struct platform_device *pdev)
>=20
>  	/* NOTE: RTIC detection ought to go here, around Si time */
>=20
> -	caam_id =3D (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
> -		  (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
> +	caam_id =3D (u64)rd_reg32(&perfmon->caam_id_ms) << 32 |
> +		  (u64)rd_reg32(&perfmon->caam_id_ls);
>=20
>  	/* Report "alive" for developer to see */
>  	dev_info(dev, "device ID =3D 0x%016llx (Era %d)\n", caam_id, diff --git
> a/drivers/crypto/caam/debugfs.c b/drivers/crypto/caam/debugfs.c index
> 806bb20d2aa1..73fe8530c0d6 100644
> --- a/drivers/crypto/caam/debugfs.c
> +++ b/drivers/crypto/caam/debugfs.c
> @@ -1,5 +1,5 @@
>  // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> -/* Copyright 2019 NXP */
> +/* Copyright 2019, 2023 NXP */
>=20
>  #include <linux/debugfs.h>
>  #include "compat.h"
> @@ -42,16 +42,14 @@ void caam_debugfs_qi_init(struct caam_drv_private
> *ctrlpriv)  }  #endif
>=20
> -void caam_debugfs_init(struct caam_drv_private *ctrlpriv, struct dentry =
*root)
> +void caam_debugfs_init(struct caam_drv_private *ctrlpriv,
> +		       struct caam_perfmon *perfmon, struct dentry *root)
>  {
> -	struct caam_perfmon *perfmon;
> -
>  	/*
>  	 * FIXME: needs better naming distinction, as some amalgamation of
>  	 * "caam" and nprop->full_name. The OF name isn't distinctive,
>  	 * but does separate instances
>  	 */
> -	perfmon =3D (struct caam_perfmon __force *)&ctrlpriv->ctrl->perfmon;
>=20
>  	ctrlpriv->ctl =3D debugfs_create_dir("ctl", root);
>=20
> diff --git a/drivers/crypto/caam/debugfs.h b/drivers/crypto/caam/debugfs.=
h
> index 661d768acdbf..fd2f0fc46d53 100644
> --- a/drivers/crypto/caam/debugfs.h
> +++ b/drivers/crypto/caam/debugfs.h
> @@ -1,16 +1,19 @@
>  /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
> -/* Copyright 2019 NXP */
> +/* Copyright 2019, 2023 NXP */
>=20
>  #ifndef CAAM_DEBUGFS_H
>  #define CAAM_DEBUGFS_H
>=20
>  struct dentry;
>  struct caam_drv_private;
> +struct caam_perfmon;
>=20
>  #ifdef CONFIG_DEBUG_FS
> -void caam_debugfs_init(struct caam_drv_private *ctrlpriv, struct dentry =
*root);
> +void caam_debugfs_init(struct caam_drv_private *ctrlpriv,
> +		       struct caam_perfmon *perfmon, struct dentry *root);
>  #else
>  static inline void caam_debugfs_init(struct caam_drv_private *ctrlpriv,
> +				     struct caam_perfmon *perfmon,
>  				     struct dentry *root)
>  {}
>  #endif
> --
> 2.25.1