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[2620:137:e000::1:20]) by mx.google.com with ESMTP id d17-20020a170902729100b001ab0498403fsi8084825pll.169.2023.05.08.13.09.19; Mon, 08 May 2023 13:09:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=EHzSlJFL; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234000AbjEHUIN (ORCPT + 99 others); Mon, 8 May 2023 16:08:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233815AbjEHUH7 (ORCPT ); Mon, 8 May 2023 16:07:59 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE0B56598; Mon, 8 May 2023 13:07:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683576472; x=1715112472; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/c7K9mHlTLpNQ6n5p6hJXCXC+v9mwx4ANeUBizx7FVM=; b=EHzSlJFLYXl59vn3fXEyPVWsgAIfbp1qQDun8yugfunzrfMSNnZ3EqUK rnW+R/7fY4/LZvpDqDlLv6gMHNWTB0hVxhDkkQZpK4KJ8x6mlJrEqSFEq PJBhA/ihpLAnkxBPeFKfsOjpwKb37ebNq09Kn21XcHA1qhfx7d9Ut7w/A L3y8ltvzev0l0sWEQOl/V/vam44XMGXweG8bGgthuxyukonrFjcKvn4SA jH0O+f/OqX9TJ1Gzwkbjg3DfKFVmUWsxAw6B4c1XtGc1TeJnwbgERsFr6 TOpmPKuWSmMv7T/Tslz6vBsGhI3FGXPrPoAhG+aNmZea3nenB8fden3n6 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10704"; a="348573647" X-IronPort-AV: E=Sophos;i="5.99,259,1677571200"; d="scan'208";a="348573647" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 13:07:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10704"; a="788241640" X-IronPort-AV: E=Sophos;i="5.99,259,1677571200"; d="scan'208";a="788241640" Received: from sajmal-mobl1.amr.corp.intel.com (HELO tzanussi-mobl1.intel.com) ([10.212.74.4]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 13:07:51 -0700 From: Tom Zanussi To: herbert@gondor.apana.org.au, davem@davemloft.net, fenghua.yu@intel.com, vkoul@kernel.org Cc: dave.jiang@intel.com, tony.luck@intel.com, wajdi.k.feghali@intel.com, james.guilford@intel.com, kanchana.p.sridhar@intel.com, giovanni.cabiddu@intel.com, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org Subject: [PATCH v4 06/15] dmaengine: idxd: Add wq private data accessors Date: Mon, 8 May 2023 15:07:28 -0500 Message-Id: <038db785a87dc59c0073989633eee0205958cb67.1683573703.git.zanussi@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Add the accessors set_idxd_wq_private() and idxd_wq_private() allowing users to set and retrieve a private void * associated with an idxd_wq. The private data is stored in the idxd_dev.conf_dev associated with each idxd_wq. Signed-off-by: Tom Zanussi --- drivers/dma/idxd/idxd.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/dma/idxd/idxd.h b/drivers/dma/idxd/idxd.h index 193552dea224..71cd4ca7d27a 100644 --- a/drivers/dma/idxd/idxd.h +++ b/drivers/dma/idxd/idxd.h @@ -552,6 +552,16 @@ static inline int idxd_wq_refcount(struct idxd_wq *wq) return wq->client_count; }; +static inline void set_idxd_wq_private(struct idxd_wq *wq, void *private) +{ + dev_set_drvdata(wq_confdev(wq), private); +} + +static inline void *idxd_wq_private(struct idxd_wq *wq) +{ + return dev_get_drvdata(wq_confdev(wq)); +} + /* * Intel IAA does not support batch processing. * The max batch size of device, max batch size of wq and -- 2.34.1