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Date:   Thu, 14 Sep 2023 13:49:14 +0100
From:   Conor Dooley <conor.dooley@microchip.com>
To:     =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= <bjorn@kernel.org>
CC:     Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        <linux-riscv@lists.infradead.org>,
        Andy Chiu <andy.chiu@sifive.com>,
        Greentime Hu <greentime.hu@sifive.com>,
        "Jason A . Donenfeld" <Jason@zx2c4.com>,
        Samuel Neves <sneves@dei.uc.pt>,
        =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= <bjorn@rivosinc.com>,
        Heiko Stuebner <heiko@sntech.de>,
        Herbert Xu <herbert@gondor.apana.org.au>,
        "David S. Miller" <davem@davemloft.net>,
        <linux-crypto@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [RFC PATCH 0/6] RISC-V BLAKE2s Vector implementation
Message-ID: <20230914-roaming-plunging-948c78d9831c@wendy>
References: <20230912115728.172982-1-bjorn@kernel.org>
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On Tue, Sep 12, 2023 at 01:57:22PM +0200, Bj=F6rn T=F6pel wrote:
> From: Bj=F6rn T=F6pel <bjorn@rivosinc.com>
>=20
> Hi,
>=20
> This is Andy's kernel mode vector V2 series [1], with my BLAKE2s
> AVX-512-to-RISC-V translation patch appended.
>=20
> I've tagged it as RFC, since Andy's series is still not in-tree yet.
>=20
> It's a first step towards a Vector aided Wireguard! ;-)

This has the same problems as Andy's stuff & doesn't build properly for the
automation. What is the plan between yourself and Andy for submitting a
version of the in-kernel vector support that passes build testing?

Cheers,
Conor.

>=20
>=20
> Cheers,
> Bj=F6rn
>=20
> [1] https://lore.kernel.org/linux-riscv/20230721112855.1006-1-andy.chiu@s=
ifive.com/
>=20
> Andy Chiu (3):
>   riscv: sched: defer restoring Vector context for user
>   riscv: vector: do not pass task_struct into
>     riscv_v_vstate_{save,restore}()
>   riscv: vector: allow kernel-mode Vector with preemption
>=20
> Bj=F6rn T=F6pel (1):
>   riscv: Add BLAKE2s V implementation
>=20
> Greentime Hu (2):
>   riscv: Add support for kernel mode vector
>   riscv: Add vector extension XOR implementation
>=20
>  arch/riscv/Kbuild                      |   2 +-
>  arch/riscv/Kconfig                     |  10 ++
>  arch/riscv/crypto/Kconfig              |  16 +++
>  arch/riscv/crypto/Makefile             |   6 +
>  arch/riscv/crypto/blake2s-glue.c       |  39 ++++++
>  arch/riscv/crypto/blake2s-v.S          | 164 +++++++++++++++++++++++++
>  arch/riscv/include/asm/entry-common.h  |  13 ++
>  arch/riscv/include/asm/processor.h     |   2 +
>  arch/riscv/include/asm/simd.h          |  52 ++++++++
>  arch/riscv/include/asm/thread_info.h   |   6 +
>  arch/riscv/include/asm/vector.h        |  50 ++++++--
>  arch/riscv/include/asm/xor.h           |  82 +++++++++++++
>  arch/riscv/kernel/Makefile             |   1 +
>  arch/riscv/kernel/asm-offsets.c        |   2 +
>  arch/riscv/kernel/entry.S              |  45 +++++++
>  arch/riscv/kernel/kernel_mode_vector.c | 146 ++++++++++++++++++++++
>  arch/riscv/kernel/process.c            |  10 +-
>  arch/riscv/kernel/ptrace.c             |   2 +-
>  arch/riscv/kernel/signal.c             |   4 +-
>  arch/riscv/kernel/vector.c             |   5 +-
>  arch/riscv/lib/Makefile                |   1 +
>  arch/riscv/lib/xor.S                   |  81 ++++++++++++
>  crypto/Kconfig                         |   3 +
>  drivers/net/Kconfig                    |   1 +
>  24 files changed, 725 insertions(+), 18 deletions(-)
>  create mode 100644 arch/riscv/crypto/Kconfig
>  create mode 100644 arch/riscv/crypto/Makefile
>  create mode 100644 arch/riscv/crypto/blake2s-glue.c
>  create mode 100644 arch/riscv/crypto/blake2s-v.S
>  create mode 100644 arch/riscv/include/asm/simd.h
>  create mode 100644 arch/riscv/include/asm/xor.h
>  create mode 100644 arch/riscv/kernel/kernel_mode_vector.c
>  create mode 100644 arch/riscv/lib/xor.S
>=20
>=20
> base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d
> --=20
> 2.39.2
>=20

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