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Date:   Mon, 16 Oct 2023 07:02:00 -0700
From:   Jakub Kicinski <kuba@kernel.org>
To:     Srujana Challa <schalla@marvell.com>
Cc:     <herbert@gondor.apana.org.au>, <davem@davemloft.net>,
        <linux-crypto@vger.kernel.org>, <bbrezillon@kernel.org>,
        <arno@natisbad.org>, <ndabilpuram@marvell.com>
Subject: Re: [PATCH 03/10] crypto: octeontx2: add devlink option to set
 max_rxc_icb_cnt
Message-ID: <20231016070200.6f18ede4@kernel.org>
In-Reply-To: <20231016064934.1913964-4-schalla@marvell.com>
References: <20231016064934.1913964-1-schalla@marvell.com>
        <20231016064934.1913964-4-schalla@marvell.com>
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On Mon, 16 Oct 2023 12:19:27 +0530 Srujana Challa wrote:
> On CN10KA B0/CN10KB HW, maximum icb entries that RX can use,
> can be configured through HW CSR. This patch adds option
> to set max icb entries through devlink parameter and also sets
> max_rxc_icb_cnt to 0xc0 as default to match inline
> inbound peak performance compared to other chip versions.

If it's a resource it should be configured via devlink-resource.

Every piece of devlink config must be documented under Documentation/

When you repost please CC netdev.