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[139.178.88.99]) by mx.google.com with ESMTPS id i13-20020a170902c94d00b001c754f13381si5856673pla.455.2023.12.11.00.13.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Dec 2023 00:13:05 -0800 (PST) Received-SPF: pass (google.com: domain of linux-crypto+bounces-690-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99; Authentication-Results: mx.google.com; dkim=pass header.i=@broadcom.com header.s=google header.b="e1aSkk/O"; spf=pass (google.com: domain of linux-crypto+bounces-690-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-crypto+bounces-690-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 061C4280D5A for ; Mon, 11 Dec 2023 08:13:05 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6E5F420DCC; Mon, 11 Dec 2023 08:12:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="e1aSkk/O" X-Original-To: linux-crypto@vger.kernel.org Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E0A0FD for ; Mon, 11 Dec 2023 00:12:39 -0800 (PST) Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-50c222a022dso4251923e87.1 for ; Mon, 11 Dec 2023 00:12:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1702282357; x=1702887157; darn=vger.kernel.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=UPPrW/w5OHLqEgBKsxvx8+8lauP/f1TUEs1UpZp0c8M=; b=e1aSkk/Ov7fjNJd/7lC/QS1HX+rqPxtj09q8bN3iwKumsWr+rTKAGDxaYwVdgynIah NXDOfoyev09Itb9coavYLfR0VboMvbFmx0GMdLiOXcsswoSL0iGUNXw3ndMKIRlizjfL N0QoztjQiUTeaFh6twG+rvPybw586vt+tx2CY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702282357; x=1702887157; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=UPPrW/w5OHLqEgBKsxvx8+8lauP/f1TUEs1UpZp0c8M=; b=aDDPKX5Weke+YyvOlKaCgTG+gTWz+JbzX/Dr5kIYYcV4MFzTj7tczUvi1dVQxABQ2j cPRW7L+qMoZhMFGiHgrbDnAycrX2g1ZgIVhLnzDHMuy+PGsbg0V54i9VYzZE9602/H5O KsgrVVM37B2cjf8yHE3KaJKpr3RQkRkvPQOJeKDxqbD4y/k89gsjJKQ9X9aNiZFIEfsR HbJ/Fo+dJYtKIv/gdiXjYnp9OyEToecvxxql7KB8YePTd6jabR8LJbUB+RxUFbvmkFqE 0gvOsCbdQM+Led8vvsUu9giwBKZtNckgvHWheGbI5XT7tISon7iASYSCkzRe2wh7ee71 JREg== X-Gm-Message-State: AOJu0YzaMZ+H2vRX53LllpzHZKWkH7rua8loASbk8aF7LsMqekG9HMbQ IYE814OGOlu9v4v6bVEjWd9qqVtIU3DrKKHiyVCwW8YdBA2o3BxI X-Received: by 2002:a19:4341:0:b0:50b:e7b4:6d17 with SMTP id m1-20020a194341000000b0050be7b46d17mr1555620lfj.56.1702282357404; Mon, 11 Dec 2023 00:12:37 -0800 (PST) Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20231211071913.151225-1-schalla@marvell.com> <20231211071913.151225-3-schalla@marvell.com> In-Reply-To: <20231211071913.151225-3-schalla@marvell.com> From: Kalesh Anakkur Purayil Date: Mon, 11 Dec 2023 13:42:25 +0530 Message-ID: Subject: Re: [PATCH net-next v1 02/10] :crypto: octeontx2: add SGv2 support for CN10KB or CN10KA B0 To: Srujana Challa Cc: herbert@gondor.apana.org.au, davem@davemloft.net, kuba@kernel.org, linux-crypto@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, bbrezillon@kernel.org, arno@natisbad.org, pabeni@redhat.com, edumazet@google.com, corbet@lwn.net, sgoutham@marvell.com, bbhushan2@marvell.com, jerinj@marvell.com, sbhatta@marvell.com, hkelam@marvell.com, lcherian@marvell.com, gakula@marvell.com, ndabilpuram@marvell.com Content-Type: multipart/signed; protocol="application/pkcs7-signature"; micalg=sha-256; boundary="000000000000412dd1060c377f53" --000000000000412dd1060c377f53 Content-Type: multipart/alternative; boundary="00000000000038e9b0060c377f60" --00000000000038e9b0060c377f60 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Srujana, Looks like you ignored my comments on V1 of your patch. On Mon, Dec 11, 2023 at 12:50=E2=80=AFPM Srujana Challa wrote: > Scatter Gather input format for CPT has changed on CN10KB/CN10KA B0 HW > to make it comapatible with NIX Scatter Gather format to support SG mode > for inline IPsec. This patch modifies the code to make the driver works > for the same. This patch also enables CPT firmware load for these chips. > > Signed-off-by: Srujana Challa > --- > drivers/crypto/marvell/octeontx2/cn10k_cpt.c | 19 +- > drivers/crypto/marvell/octeontx2/cn10k_cpt.h | 1 + > .../marvell/octeontx2/otx2_cpt_common.h | 41 ++- > .../marvell/octeontx2/otx2_cpt_hw_types.h | 3 + > .../marvell/octeontx2/otx2_cpt_reqmgr.h | 293 ++++++++++++++++++ > drivers/crypto/marvell/octeontx2/otx2_cptlf.h | 2 + > .../marvell/octeontx2/otx2_cptpf_main.c | 26 +- > .../marvell/octeontx2/otx2_cptpf_mbox.c | 2 +- > .../marvell/octeontx2/otx2_cptpf_ucode.c | 33 +- > .../marvell/octeontx2/otx2_cptpf_ucode.h | 3 +- > drivers/crypto/marvell/octeontx2/otx2_cptvf.h | 2 + > .../marvell/octeontx2/otx2_cptvf_main.c | 13 + > .../marvell/octeontx2/otx2_cptvf_mbox.c | 26 ++ > .../marvell/octeontx2/otx2_cptvf_reqmgr.c | 160 +--------- > 14 files changed, 447 insertions(+), 177 deletions(-) > > diff --git a/drivers/crypto/marvell/octeontx2/cn10k_cpt.c > b/drivers/crypto/marvell/octeontx2/cn10k_cpt.c > index 93d22b328991..b23ae3a020e0 100644 > --- a/drivers/crypto/marvell/octeontx2/cn10k_cpt.c > +++ b/drivers/crypto/marvell/octeontx2/cn10k_cpt.c > @@ -14,12 +14,14 @@ static struct cpt_hw_ops otx2_hw_ops =3D { > .send_cmd =3D otx2_cpt_send_cmd, > .cpt_get_compcode =3D otx2_cpt_get_compcode, > .cpt_get_uc_compcode =3D otx2_cpt_get_uc_compcode, > + .cpt_sg_info_create =3D otx2_sg_info_create, > }; > > static struct cpt_hw_ops cn10k_hw_ops =3D { > .send_cmd =3D cn10k_cpt_send_cmd, > .cpt_get_compcode =3D cn10k_cpt_get_compcode, > .cpt_get_uc_compcode =3D cn10k_cpt_get_uc_compcode, > + .cpt_sg_info_create =3D otx2_sg_info_create, > }; > > static void cn10k_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, u32 > insts_num, > @@ -78,12 +80,9 @@ int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptv= f) > struct pci_dev *pdev =3D cptvf->pdev; > resource_size_t offset, size; > > - if (!test_bit(CN10K_LMTST, &cptvf->cap_flag)) { > - cptvf->lfs.ops =3D &otx2_hw_ops; > + if (!test_bit(CN10K_LMTST, &cptvf->cap_flag)) > return 0; > - } > > - cptvf->lfs.ops =3D &cn10k_hw_ops; > offset =3D pci_resource_start(pdev, PCI_MBOX_BAR_NUM); > size =3D pci_resource_len(pdev, PCI_MBOX_BAR_NUM); > /* Map VF LMILINE region */ > @@ -96,3 +95,15 @@ int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptv= f) > return 0; > } > EXPORT_SYMBOL_NS_GPL(cn10k_cptvf_lmtst_init, CRYPTO_DEV_OCTEONTX2_CPT); > + > +int cptvf_hw_ops_get(struct otx2_cptvf_dev *cptvf) > +{ > + if (!test_bit(CN10K_LMTST, &cptvf->cap_flag)) { > + cptvf->lfs.ops =3D &otx2_hw_ops; > + return 0; > + } > + cptvf->lfs.ops =3D &cn10k_hw_ops; > + > + return 0; > +} > +EXPORT_SYMBOL_NS_GPL(cptvf_hw_ops_get, CRYPTO_DEV_OCTEONTX2_CPT); > [Kalesh]: You can make this function return void as it returns 0 always. +void cptvf_hw_ops_get(struct otx2_cptvf_dev *cptvf) +{ + if (!test_bit(CN10K_LMTST, &cptvf->cap_flag)) + cptvf->lfs.ops =3D &otx2_hw_ops; + else + cptvf->lfs.ops =3D &cn10k_hw_ops; +} > diff --git a/drivers/crypto/marvell/octeontx2/cn10k_cpt.h > b/drivers/crypto/marvell/octeontx2/cn10k_cpt.h > index aaefc7e38e06..0f714ee564f5 100644 > --- a/drivers/crypto/marvell/octeontx2/cn10k_cpt.h > +++ b/drivers/crypto/marvell/octeontx2/cn10k_cpt.h > @@ -30,5 +30,6 @@ static inline u8 otx2_cpt_get_uc_compcode(union > otx2_cpt_res_s *result) > > int cn10k_cptpf_lmtst_init(struct otx2_cptpf_dev *cptpf); > int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf); > +int cptvf_hw_ops_get(struct otx2_cptvf_dev *cptvf); > > #endif /* __CN10K_CPTLF_H */ > diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h > b/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h > index 46b778bbbee4..2a7544252444 100644 > --- a/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h > +++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h > @@ -102,7 +102,10 @@ union otx2_cpt_eng_caps { > u64 kasumi:1; > u64 des:1; > u64 crc:1; > - u64 reserved_14_63:50; > + u64 mmul:1; > + u64 reserved_15_33:19; > + u64 pdcp_chain:1; > + u64 reserved_35_63:29; > }; > }; > > @@ -145,6 +148,41 @@ static inline bool is_dev_otx2(struct pci_dev *pdev) > return false; > } > > +static inline bool is_dev_cn10ka(struct pci_dev *pdev) > +{ > + if (pdev->subsystem_device =3D=3D CPT_PCI_SUBSYS_DEVID_CN10K_A) > + return true; > + > + return false; > +} > [Kalesh]: You can further simply this as: return pdev->subsystem_device =3D=3D CPT_PCI_SUBSYS_DEVID_CN10K_A > + > +static inline bool is_dev_cn10ka_ax(struct pci_dev *pdev) > +{ > + if (pdev->subsystem_device =3D=3D CPT_PCI_SUBSYS_DEVID_CN10K_A && > + ((pdev->revision & 0xFF) =3D=3D 4 || (pdev->revision & 0xFF) = =3D=3D > 0x50 || > + (pdev->revision & 0xff) =3D=3D 0x51)) > + return true; > + > + return false; > +} > + > +static inline bool is_dev_cn10kb(struct pci_dev *pdev) > +{ > + if (pdev->subsystem_device =3D=3D CPT_PCI_SUBSYS_DEVID_CN10K_B) > + return true; > + > + return false; > +} > [Kalesh]: You can further simply this as: return pdev->subsystem_device =3D=3D CPT_PCI_SUBSYS_DEVID_CN10K_B > + > +static inline bool is_dev_cn10ka_b0(struct pci_dev *pdev) > +{ > + if (pdev->subsystem_device =3D=3D CPT_PCI_SUBSYS_DEVID_CN10K_A && > + (pdev->revision & 0xFF) =3D=3D 0x54) > + return true; > + > + return false; > +} > + > static inline void otx2_cpt_set_hw_caps(struct pci_dev *pdev, > unsigned long *cap_flag) > { > @@ -154,7 +192,6 @@ static inline void otx2_cpt_set_hw_caps(struct pci_de= v > *pdev, > } > } > > - > [Kalesh]: This change looks unrelated > int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev= ); > int otx2_cpt_send_mbox_msg(struct otx2_mbox *mbox, struct pci_dev *pdev)= ; > > diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h > b/drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h > index 6f947978e4e8..756aee0c2b05 100644 > --- a/drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h > +++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h > @@ -13,6 +13,9 @@ > #define CN10K_CPT_PCI_PF_DEVICE_ID 0xA0F2 > #define CN10K_CPT_PCI_VF_DEVICE_ID 0xA0F3 > > +#define CPT_PCI_SUBSYS_DEVID_CN10K_A 0xB900 > +#define CPT_PCI_SUBSYS_DEVID_CN10K_B 0xBD00 > + > /* Mailbox interrupts offset */ > #define OTX2_CPT_PF_MBOX_INT 6 > #define OTX2_CPT_PF_INT_VEC_E_MBOXX(x, a) ((x) + (a)) > diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h > b/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h > index dbb1ee746f4c..b0f426531a42 100644 > --- a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h > +++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h > @@ -143,6 +143,8 @@ struct otx2_cpt_inst_info { > unsigned long time_in; > u32 dlen; > u32 dma_len; > + u64 gthr_sz; > + u64 sctr_sz; > u8 extra_time; > }; > > @@ -157,6 +159,16 @@ struct otx2_cpt_sglist_component { > __be64 ptr3; > }; > > +struct cn10kb_cpt_sglist_component { > + u16 len0; > + u16 len1; > + u16 len2; > + u16 valid_segs; > + u64 ptr0; > + u64 ptr1; > + u64 ptr2; > +}; > + > static inline void otx2_cpt_info_destroy(struct pci_dev *pdev, > struct otx2_cpt_inst_info *info) > { > @@ -188,6 +200,287 @@ static inline void otx2_cpt_info_destroy(struct > pci_dev *pdev, > kfree(info); > } > > +static inline int setup_sgio_components(struct pci_dev *pdev, > + struct otx2_cpt_buf_ptr *list, > + int buf_count, u8 *buffer) > +{ > + struct otx2_cpt_sglist_component *sg_ptr =3D NULL; > + int ret =3D 0, i, j; > + int components; > + > + if (unlikely(!list)) { > + dev_err(&pdev->dev, "Input list pointer is NULL\n"); > + return -EFAULT; > + } > + > + for (i =3D 0; i < buf_count; i++) { > + if (unlikely(!list[i].vptr)) > + continue; > + list[i].dma_addr =3D dma_map_single(&pdev->dev, list[i].v= ptr, > + list[i].size, > + DMA_BIDIRECTIONAL); > + if (unlikely(dma_mapping_error(&pdev->dev, > list[i].dma_addr))) { > + dev_err(&pdev->dev, "Dma mapping failed\n"); > + ret =3D -EIO; > + goto sg_cleanup; > + } > + } > + components =3D buf_count / 4; > + sg_ptr =3D (struct otx2_cpt_sglist_component *)buffer; > + for (i =3D 0; i < components; i++) { > + sg_ptr->len0 =3D cpu_to_be16(list[i * 4 + 0].size); > + sg_ptr->len1 =3D cpu_to_be16(list[i * 4 + 1].size); > + sg_ptr->len2 =3D cpu_to_be16(list[i * 4 + 2].size); > + sg_ptr->len3 =3D cpu_to_be16(list[i * 4 + 3].size); > + sg_ptr->ptr0 =3D cpu_to_be64(list[i * 4 + 0].dma_addr); > + sg_ptr->ptr1 =3D cpu_to_be64(list[i * 4 + 1].dma_addr); > + sg_ptr->ptr2 =3D cpu_to_be64(list[i * 4 + 2].dma_addr); > + sg_ptr->ptr3 =3D cpu_to_be64(list[i * 4 + 3].dma_addr); > + sg_ptr++; > + } > + components =3D buf_count % 4; > + > + switch (components) { > + case 3: > + sg_ptr->len2 =3D cpu_to_be16(list[i * 4 + 2].size); > + sg_ptr->ptr2 =3D cpu_to_be64(list[i * 4 + 2].dma_addr); > + fallthrough; > + case 2: > + sg_ptr->len1 =3D cpu_to_be16(list[i * 4 + 1].size); > + sg_ptr->ptr1 =3D cpu_to_be64(list[i * 4 + 1].dma_addr); > + fallthrough; > + case 1: > + sg_ptr->len0 =3D cpu_to_be16(list[i * 4 + 0].size); > + sg_ptr->ptr0 =3D cpu_to_be64(list[i * 4 + 0].dma_addr); > + break; > + default: > + break; > + } > + return ret; > + > +sg_cleanup: > + for (j =3D 0; j < i; j++) { > + if (list[j].dma_addr) { > + dma_unmap_single(&pdev->dev, list[j].dma_addr, > + list[j].size, DMA_BIDIRECTIONAL)= ; > + } > + > + list[j].dma_addr =3D 0; > + } > + return ret; > +} > + > +static inline int sgv2io_components_setup(struct pci_dev *pdev, > + struct otx2_cpt_buf_ptr *list, > + int buf_count, u8 *buffer) > +{ > + struct cn10kb_cpt_sglist_component *sg_ptr =3D NULL; > + int ret =3D 0, i, j; > + int components; > [Kalesh]: maintain RCT order > + > + if (unlikely(!list)) { > + dev_err(&pdev->dev, "Input list pointer is NULL\n"); > + return -EFAULT; > + } > + > + for (i =3D 0; i < buf_count; i++) { > + if (unlikely(!list[i].vptr)) > + continue; > + list[i].dma_addr =3D dma_map_single(&pdev->dev, list[i].v= ptr, > + list[i].size, > + DMA_BIDIRECTIONAL); > + if (unlikely(dma_mapping_error(&pdev->dev, > list[i].dma_addr))) { > + dev_err(&pdev->dev, "Dma mapping failed\n"); > + ret =3D -EIO; > + goto sg_cleanup; > + } > + } > + components =3D buf_count / 3; > + sg_ptr =3D (struct cn10kb_cpt_sglist_component *)buffer; > + for (i =3D 0; i < components; i++) { > + sg_ptr->len0 =3D list[i * 3 + 0].size; > + sg_ptr->len1 =3D list[i * 3 + 1].size; > + sg_ptr->len2 =3D list[i * 3 + 2].size; > + sg_ptr->ptr0 =3D list[i * 3 + 0].dma_addr; > + sg_ptr->ptr1 =3D list[i * 3 + 1].dma_addr; > + sg_ptr->ptr2 =3D list[i * 3 + 2].dma_addr; > + sg_ptr->valid_segs =3D 3; > + sg_ptr++; > + } > + components =3D buf_count % 3; > + > + sg_ptr->valid_segs =3D components; > + switch (components) { > + case 2: > + sg_ptr->len1 =3D list[i * 3 + 1].size; > + sg_ptr->ptr1 =3D list[i * 3 + 1].dma_addr; > + fallthrough; > + case 1: > + sg_ptr->len0 =3D list[i * 3 + 0].size; > + sg_ptr->ptr0 =3D list[i * 3 + 0].dma_addr; > + break; > + default: > + break; > + } > + return ret; > + > +sg_cleanup: > + for (j =3D 0; j < i; j++) { > + if (list[j].dma_addr) { > + dma_unmap_single(&pdev->dev, list[j].dma_addr, > + list[j].size, DMA_BIDIRECTIONAL)= ; > + } > + > + list[j].dma_addr =3D 0; > + } > + return ret; > +} > + > +static inline struct otx2_cpt_inst_info *cn10k_sgv2_info_create( > + struct pci_dev *pdev, > + struct otx2_cpt_req_info > *req, > + gfp_t gfp) > +{ > + u32 dlen =3D 0, g_len, sg_len, info_len; > + int align =3D OTX2_CPT_DMA_MINALIGN; > + struct otx2_cpt_inst_info *info; > + u16 g_sz_bytes, s_sz_bytes; > + u32 total_mem_len; > + int i; > + > + g_sz_bytes =3D ((req->in_cnt + 2) / 3) * > + sizeof(struct cn10kb_cpt_sglist_component); > + s_sz_bytes =3D ((req->out_cnt + 2) / 3) * > + sizeof(struct cn10kb_cpt_sglist_component); > + > + g_len =3D ALIGN(g_sz_bytes, align); > + sg_len =3D ALIGN(g_len + s_sz_bytes, align); > + info_len =3D ALIGN(sizeof(*info), align); > + total_mem_len =3D sg_len + info_len + sizeof(union otx2_cpt_res_s= ); > + > + info =3D kzalloc(total_mem_len, gfp); > + if (unlikely(!info)) > + return NULL; > + > + for (i =3D 0; i < req->in_cnt; i++) > + dlen +=3D req->in[i].size; > + > + info->dlen =3D dlen; > + info->in_buffer =3D (u8 *)info + info_len; > + info->gthr_sz =3D req->in_cnt; > + info->sctr_sz =3D req->out_cnt; > + > + /* Setup gather (input) components */ > + if (sgv2io_components_setup(pdev, req->in, req->in_cnt, > + info->in_buffer)) { > + dev_err(&pdev->dev, "Failed to setup gather list\n"); > + goto destroy_info; > + } > + > + if (sgv2io_components_setup(pdev, req->out, req->out_cnt, > + &info->in_buffer[g_len])) { > + dev_err(&pdev->dev, "Failed to setup scatter list\n"); > + goto destroy_info; > + } > + > + info->dma_len =3D total_mem_len - info_len; > + info->dptr_baddr =3D dma_map_single(&pdev->dev, info->in_buffer, > + info->dma_len, > DMA_BIDIRECTIONAL); > + if (unlikely(dma_mapping_error(&pdev->dev, info->dptr_baddr))) { > + dev_err(&pdev->dev, "DMA Mapping failed for cpt req\n"); > + goto destroy_info; > + } > + info->rptr_baddr =3D info->dptr_baddr + g_len; > + /* > + * Get buffer for union otx2_cpt_res_s response > + * structure and its physical address > + */ > + info->completion_addr =3D info->in_buffer + sg_len; > + info->comp_baddr =3D info->dptr_baddr + sg_len; > + > + return info; > + > +destroy_info: > + otx2_cpt_info_destroy(pdev, info); > + return NULL; > +} > + > +/* SG list header size in bytes */ > +#define SG_LIST_HDR_SIZE 8 > +static inline struct otx2_cpt_inst_info *otx2_sg_info_create( > + struct pci_dev *pdev, > + struct otx2_cpt_req_info > *req, > + gfp_t gfp) > +{ > + int align =3D OTX2_CPT_DMA_MINALIGN; > + struct otx2_cpt_inst_info *info; > + u32 dlen, align_dlen, info_len; > + u16 g_sz_bytes, s_sz_bytes; > + u32 total_mem_len; > + > + if (unlikely(req->in_cnt > OTX2_CPT_MAX_SG_IN_CNT || > + req->out_cnt > OTX2_CPT_MAX_SG_OUT_CNT)) { > + dev_err(&pdev->dev, "Error too many sg components\n"); > + return NULL; > + } > + > + g_sz_bytes =3D ((req->in_cnt + 3) / 4) * > + sizeof(struct otx2_cpt_sglist_component); > + s_sz_bytes =3D ((req->out_cnt + 3) / 4) * > + sizeof(struct otx2_cpt_sglist_component); > + > + dlen =3D g_sz_bytes + s_sz_bytes + SG_LIST_HDR_SIZE; > + align_dlen =3D ALIGN(dlen, align); > + info_len =3D ALIGN(sizeof(*info), align); > + total_mem_len =3D align_dlen + info_len + sizeof(union > otx2_cpt_res_s); > + > + info =3D kzalloc(total_mem_len, gfp); > + if (unlikely(!info)) > + return NULL; > + > + info->dlen =3D dlen; > + info->in_buffer =3D (u8 *)info + info_len; > + > + ((u16 *)info->in_buffer)[0] =3D req->out_cnt; > + ((u16 *)info->in_buffer)[1] =3D req->in_cnt; > + ((u16 *)info->in_buffer)[2] =3D 0; > + ((u16 *)info->in_buffer)[3] =3D 0; > + cpu_to_be64s((u64 *)info->in_buffer); > + > + /* Setup gather (input) components */ > + if (setup_sgio_components(pdev, req->in, req->in_cnt, > + &info->in_buffer[8])) { > + dev_err(&pdev->dev, "Failed to setup gather list\n"); > + goto destroy_info; > + } > + > + if (setup_sgio_components(pdev, req->out, req->out_cnt, > + &info->in_buffer[8 + g_sz_bytes])) { > + dev_err(&pdev->dev, "Failed to setup scatter list\n"); > + goto destroy_info; > + } > + > + info->dma_len =3D total_mem_len - info_len; > + info->dptr_baddr =3D dma_map_single(&pdev->dev, info->in_buffer, > + info->dma_len, > DMA_BIDIRECTIONAL); > + if (unlikely(dma_mapping_error(&pdev->dev, info->dptr_baddr))) { > + dev_err(&pdev->dev, "DMA Mapping failed for cpt req\n"); > + goto destroy_info; > + } > + /* > + * Get buffer for union otx2_cpt_res_s response > + * structure and its physical address > + */ > + info->completion_addr =3D info->in_buffer + align_dlen; > + info->comp_baddr =3D info->dptr_baddr + align_dlen; > + > + return info; > + > +destroy_info: > + otx2_cpt_info_destroy(pdev, info); > [Kalesh]" Where is the memory allocated for "info" getting freed. The memory is allocated locally inside this function. > + return NULL; > +} > + > struct otx2_cptlf_wqe; > int otx2_cpt_do_request(struct pci_dev *pdev, struct otx2_cpt_req_info > *req, > int cpu_num); > diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptlf.h > b/drivers/crypto/marvell/octeontx2/otx2_cptlf.h > index 5302fe3d0e6f..70138d65ba9e 100644 > --- a/drivers/crypto/marvell/octeontx2/otx2_cptlf.h > +++ b/drivers/crypto/marvell/octeontx2/otx2_cptlf.h > @@ -99,6 +99,8 @@ struct cpt_hw_ops { > struct otx2_cptlf_info *lf); > u8 (*cpt_get_compcode)(union otx2_cpt_res_s *result); > u8 (*cpt_get_uc_compcode)(union otx2_cpt_res_s *result); > + struct otx2_cpt_inst_info * (*cpt_sg_info_create)(struct pci_dev > *pdev, > + struct otx2_cpt_req_info *req, gfp_t > gfp); > }; > > struct otx2_cptlfs_info { > diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c > b/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c > index 5436b0d3685c..c64c50a964ed 100644 > --- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c > +++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c > @@ -14,6 +14,8 @@ > #define OTX2_CPT_DRV_STRING "Marvell RVU CPT Physical Function Driver" > > #define CPT_UC_RID_CN9K_B0 1 > +#define CPT_UC_RID_CN10K_A 4 > +#define CPT_UC_RID_CN10K_B 5 > > static void cptpf_enable_vfpf_mbox_intr(struct otx2_cptpf_dev *cptpf, > int num_vfs) > @@ -587,6 +589,26 @@ static int cpt_is_pf_usable(struct otx2_cptpf_dev > *cptpf) > return 0; > } > > +static int cptpf_get_rid(struct pci_dev *pdev, struct otx2_cptpf_dev > *cptpf) > +{ > + struct otx2_cpt_eng_grps *eng_grps =3D &cptpf->eng_grps; > + u64 reg_val =3D 0x0; > + > + if (is_dev_otx2(pdev)) { > + eng_grps->rid =3D pdev->revision; > + return 0; > + } > + otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL, ®_va= l, > + BLKADDR_CPT0); > + if ((is_dev_cn10ka_b0(pdev) && (reg_val & BIT_ULL(18))) || > + is_dev_cn10ka_ax(pdev)) > + eng_grps->rid =3D CPT_UC_RID_CN10K_A; > + else if (is_dev_cn10kb(pdev) || is_dev_cn10ka_b0(pdev)) > + eng_grps->rid =3D CPT_UC_RID_CN10K_B; > + > + return 0; > +} > [Kalesh]: You can convert this function to return void as it always returns 0 always. > + > static void cptpf_check_block_implemented(struct otx2_cptpf_dev *cptpf) > { > u64 cfg; > @@ -657,7 +679,9 @@ static int cptpf_sriov_enable(struct pci_dev *pdev, > int num_vfs) > ret =3D cptpf_register_vfpf_intr(cptpf, num_vfs); > if (ret) > goto destroy_flr; > - > + ret =3D cptpf_get_rid(pdev, cptpf); > + if (ret) > + goto disable_intr; > /* Get CPT HW capabilities using LOAD_FVC operation. */ > ret =3D otx2_cpt_discover_eng_capabilities(cptpf); > if (ret) > diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c > b/drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c > index 480b3720f15a..390ed146d309 100644 > --- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c > +++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c > @@ -78,7 +78,7 @@ static int handle_msg_get_caps(struct otx2_cptpf_dev > *cptpf, > rsp->hdr.sig =3D OTX2_MBOX_RSP_SIG; > rsp->hdr.pcifunc =3D req->pcifunc; > rsp->cpt_pf_drv_version =3D OTX2_CPT_PF_DRV_VERSION; > - rsp->cpt_revision =3D cptpf->pdev->revision; > + rsp->cpt_revision =3D cptpf->eng_grps.rid; > memcpy(&rsp->eng_caps, &cptpf->eng_caps, sizeof(rsp->eng_caps)); > > return 0; > diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c > b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c > index 1958b797a421..7fccc348f66e 100644 > --- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c > +++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c > @@ -117,12 +117,10 @@ static char *get_ucode_type_str(int ucode_type) > > static int get_ucode_type(struct device *dev, > struct otx2_cpt_ucode_hdr *ucode_hdr, > - int *ucode_type) > + int *ucode_type, u16 rid) > { > - struct otx2_cptpf_dev *cptpf =3D dev_get_drvdata(dev); > char ver_str_prefix[OTX2_CPT_UCODE_VER_STR_SZ]; > char tmp_ver_str[OTX2_CPT_UCODE_VER_STR_SZ]; > - struct pci_dev *pdev =3D cptpf->pdev; > int i, val =3D 0; > u8 nn; > > @@ -130,7 +128,7 @@ static int get_ucode_type(struct device *dev, > for (i =3D 0; i < strlen(tmp_ver_str); i++) > tmp_ver_str[i] =3D tolower(tmp_ver_str[i]); > > - sprintf(ver_str_prefix, "ocpt-%02d", pdev->revision); > + sprintf(ver_str_prefix, "ocpt-%02d", rid); > if (!strnstr(tmp_ver_str, ver_str_prefix, > OTX2_CPT_UCODE_VER_STR_SZ)) > return -EINVAL; > > @@ -359,7 +357,7 @@ static int cpt_attach_and_enable_cores(struct > otx2_cpt_eng_grp_info *eng_grp, > } > > static int load_fw(struct device *dev, struct fw_info_t *fw_info, > - char *filename) > + char *filename, u16 rid) > { > struct otx2_cpt_ucode_hdr *ucode_hdr; > struct otx2_cpt_uc_info_t *uc_info; > @@ -375,7 +373,7 @@ static int load_fw(struct device *dev, struct > fw_info_t *fw_info, > goto free_uc_info; > > ucode_hdr =3D (struct otx2_cpt_ucode_hdr *)uc_info->fw->data; > - ret =3D get_ucode_type(dev, ucode_hdr, &ucode_type); > + ret =3D get_ucode_type(dev, ucode_hdr, &ucode_type, rid); > if (ret) > goto release_fw; > > @@ -389,6 +387,7 @@ static int load_fw(struct device *dev, struct > fw_info_t *fw_info, > set_ucode_filename(&uc_info->ucode, filename); > memcpy(uc_info->ucode.ver_str, ucode_hdr->ver_str, > OTX2_CPT_UCODE_VER_STR_SZ); > + uc_info->ucode.ver_str[OTX2_CPT_UCODE_VER_STR_SZ] =3D 0; > uc_info->ucode.ver_num =3D ucode_hdr->ver_num; > uc_info->ucode.type =3D ucode_type; > uc_info->ucode.size =3D ucode_size; > @@ -448,7 +447,8 @@ static void print_uc_info(struct fw_info_t *fw_info) > } > } > > -static int cpt_ucode_load_fw(struct pci_dev *pdev, struct fw_info_t > *fw_info) > +static int cpt_ucode_load_fw(struct pci_dev *pdev, struct fw_info_t > *fw_info, > + u16 rid) > { > char filename[OTX2_CPT_NAME_LENGTH]; > char eng_type[8] =3D {0}; > @@ -462,9 +462,9 @@ static int cpt_ucode_load_fw(struct pci_dev *pdev, > struct fw_info_t *fw_info) > eng_type[i] =3D tolower(eng_type[i]); > > snprintf(filename, sizeof(filename), "mrvl/cpt%02d/%s.out= ", > - pdev->revision, eng_type); > + rid, eng_type); > /* Request firmware for each engine type */ > - ret =3D load_fw(&pdev->dev, fw_info, filename); > + ret =3D load_fw(&pdev->dev, fw_info, filename, rid); > if (ret) > goto release_fw; > } > @@ -1155,7 +1155,7 @@ int otx2_cpt_create_eng_grps(struct otx2_cptpf_dev > *cptpf, > if (eng_grps->is_grps_created) > goto unlock; > > - ret =3D cpt_ucode_load_fw(pdev, &fw_info); > + ret =3D cpt_ucode_load_fw(pdev, &fw_info, eng_grps->rid); > if (ret) > goto unlock; > > @@ -1230,14 +1230,16 @@ int otx2_cpt_create_eng_grps(struct otx2_cptpf_de= v > *cptpf, > */ > rnm_to_cpt_errata_fixup(&pdev->dev); > > + otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL, ®_va= l, > + BLKADDR_CPT0); > /* > * Configure engine group mask to allow context prefetching > * for the groups and enable random number request, to enable > * CPT to request random numbers from RNM. > */ > + reg_val |=3D OTX2_CPT_ALL_ENG_GRPS_MASK << 3 | BIT_ULL(16); > otx2_cpt_write_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL, > - OTX2_CPT_ALL_ENG_GRPS_MASK << 3 | > BIT_ULL(16), > - BLKADDR_CPT0); > + reg_val, BLKADDR_CPT0); > /* > * Set interval to periodically flush dirty data for the next > * CTX cache entry. Set the interval count to maximum supported > @@ -1412,7 +1414,7 @@ static int create_eng_caps_discovery_grps(struct > pci_dev *pdev, > int ret; > > mutex_lock(&eng_grps->lock); > - ret =3D cpt_ucode_load_fw(pdev, &fw_info); > + ret =3D cpt_ucode_load_fw(pdev, &fw_info, eng_grps->rid); > if (ret) { > mutex_unlock(&eng_grps->lock); > return ret; > @@ -1686,13 +1688,14 @@ int otx2_cpt_dl_custom_egrp_create(struct > otx2_cptpf_dev *cptpf, > goto err_unlock; > } > INIT_LIST_HEAD(&fw_info.ucodes); > - ret =3D load_fw(dev, &fw_info, ucode_filename[0]); > + > + ret =3D load_fw(dev, &fw_info, ucode_filename[0], eng_grps->rid); > if (ret) { > dev_err(dev, "Unable to load firmware %s\n", > ucode_filename[0]); > goto err_unlock; > } > if (ucode_idx > 1) { > - ret =3D load_fw(dev, &fw_info, ucode_filename[1]); > + ret =3D load_fw(dev, &fw_info, ucode_filename[1], > eng_grps->rid); > if (ret) { > dev_err(dev, "Unable to load firmware %s\n", > ucode_filename[1]); > diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h > b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h > index e69320a54b5d..365fe8943bd9 100644 > --- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h > +++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h > @@ -73,7 +73,7 @@ struct otx2_cpt_ucode_hdr { > }; > > struct otx2_cpt_ucode { > - u8 ver_str[OTX2_CPT_UCODE_VER_STR_SZ];/* > + u8 ver_str[OTX2_CPT_UCODE_VER_STR_SZ + 1];/* > * ucode version in readabl= e > * format > */ > @@ -150,6 +150,7 @@ struct otx2_cpt_eng_grps { > int engs_num; /* total number of engines > supported */ > u8 eng_ref_cnt[OTX2_CPT_MAX_ENGINES];/* engines reference count *= / > bool is_grps_created; /* Is the engine groups are already created > */ > + u16 rid; > }; > struct otx2_cptpf_dev; > int otx2_cpt_init_eng_grps(struct pci_dev *pdev, > diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf.h > b/drivers/crypto/marvell/octeontx2/otx2_cptvf.h > index 994291e90da1..11ab9af1df15 100644 > --- a/drivers/crypto/marvell/octeontx2/otx2_cptvf.h > +++ b/drivers/crypto/marvell/octeontx2/otx2_cptvf.h > @@ -22,6 +22,7 @@ struct otx2_cptvf_dev { > int blkaddr; > void *bbuf_base; > unsigned long cap_flag; > + u64 eng_caps[OTX2_CPT_MAX_ENG_TYPES]; > }; > > irqreturn_t otx2_cptvf_pfvf_mbox_intr(int irq, void *arg); > @@ -29,5 +30,6 @@ void otx2_cptvf_pfvf_mbox_handler(struct work_struct > *work); > int otx2_cptvf_send_eng_grp_num_msg(struct otx2_cptvf_dev *cptvf, int > eng_type); > int otx2_cptvf_send_kvf_limits_msg(struct otx2_cptvf_dev *cptvf); > int otx2_cpt_mbox_bbuf_init(struct otx2_cptvf_dev *cptvf, struct pci_dev > *pdev); > +int otx2_cptvf_send_caps_msg(struct otx2_cptvf_dev *cptvf); > > #endif /* __OTX2_CPTVF_H */ > diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c > b/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c > index bac729c885f9..5d1e11135c17 100644 > --- a/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c > +++ b/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c > @@ -380,6 +380,19 @@ static int otx2_cptvf_probe(struct pci_dev *pdev, > goto destroy_pfvf_mbox; > > cptvf->blkaddr =3D BLKADDR_CPT0; > + > + ret =3D cptvf_hw_ops_get(cptvf); > + if (ret) > + goto unregister_interrupts; > [Kalesh]: No need to check return value here. See my other comment above. > + > + ret =3D otx2_cptvf_send_caps_msg(cptvf); > + if (ret) { > + dev_err(&pdev->dev, "Couldn't get CPT engine > capabilities.\n"); > + goto unregister_interrupts; > + } > + if (cptvf->eng_caps[OTX2_CPT_SE_TYPES] & BIT_ULL(35)) > + cptvf->lfs.ops->cpt_sg_info_create =3D > cn10k_sgv2_info_create; > + > /* Initialize CPT LFs */ > ret =3D cptvf_lf_init(cptvf); > if (ret) > diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c > b/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c > index 75c403f2b1d9..f68da1d08fdf 100644 > --- a/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c > +++ b/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c > @@ -72,6 +72,7 @@ static void process_pfvf_mbox_mbox_msg(struct > otx2_cptvf_dev *cptvf, > struct otx2_cptlfs_info *lfs =3D &cptvf->lfs; > struct otx2_cpt_kvf_limits_rsp *rsp_limits; > struct otx2_cpt_egrp_num_rsp *rsp_grp; > + struct otx2_cpt_caps_rsp *eng_caps; > struct cpt_rd_wr_reg_msg *rsp_reg; > struct msix_offset_rsp *rsp_msix; > int i; > @@ -127,6 +128,11 @@ static void process_pfvf_mbox_mbox_msg(struct > otx2_cptvf_dev *cptvf, > rsp_limits =3D (struct otx2_cpt_kvf_limits_rsp *) msg; > cptvf->lfs.kvf_limits =3D rsp_limits->kvf_limits; > break; > + case MBOX_MSG_GET_CAPS: > + eng_caps =3D (struct otx2_cpt_caps_rsp *)msg; > + memcpy(cptvf->eng_caps, eng_caps->eng_caps, > + sizeof(cptvf->eng_caps)); > + break; > default: > dev_err(&cptvf->pdev->dev, "Unsupported msg %d > received.\n", > msg->id); > @@ -205,3 +211,23 @@ int otx2_cptvf_send_kvf_limits_msg(struct > otx2_cptvf_dev *cptvf) > > return otx2_cpt_send_mbox_msg(mbox, pdev); > } > + > +int otx2_cptvf_send_caps_msg(struct otx2_cptvf_dev *cptvf) > +{ > + struct otx2_mbox *mbox =3D &cptvf->pfvf_mbox; > + struct pci_dev *pdev =3D cptvf->pdev; > + struct mbox_msghdr *req; > + > + req =3D (struct mbox_msghdr *) > + otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req), > + sizeof(struct otx2_cpt_caps_rsp)); > + if (!req) { > + dev_err(&pdev->dev, "RVU MBOX failed to get message.\n"); > + return -EFAULT; > + } > + req->id =3D MBOX_MSG_GET_CAPS; > + req->sig =3D OTX2_MBOX_REQ_SIG; > + req->pcifunc =3D OTX2_CPT_RVU_PFFUNC(cptvf->vf_id, 0); > + > + return otx2_cpt_send_mbox_msg(mbox, pdev); > +} > diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c > b/drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c > index 811ded72ce5f..997a2eb60c66 100644 > --- a/drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c > +++ b/drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c > @@ -4,9 +4,6 @@ > #include "otx2_cptvf.h" > #include "otx2_cpt_common.h" > > -/* SG list header size in bytes */ > -#define SG_LIST_HDR_SIZE 8 > - > /* Default timeout when waiting for free pending entry in us */ > #define CPT_PENTRY_TIMEOUT 1000 > #define CPT_PENTRY_STEP 50 > @@ -26,9 +23,9 @@ static void otx2_cpt_dump_sg_list(struct pci_dev *pdev, > > pr_debug("Gather list size %d\n", req->in_cnt); > for (i =3D 0; i < req->in_cnt; i++) { > - pr_debug("Buffer %d size %d, vptr 0x%p, dmaptr 0x%p\n", i= , > + pr_debug("Buffer %d size %d, vptr 0x%p, dmaptr 0x%llx\n", > i, > req->in[i].size, req->in[i].vptr, > - (void *) req->in[i].dma_addr); > + req->in[i].dma_addr); > pr_debug("Buffer hexdump (%d bytes)\n", > req->in[i].size); > print_hex_dump_debug("", DUMP_PREFIX_NONE, 16, 1, > @@ -36,9 +33,9 @@ static void otx2_cpt_dump_sg_list(struct pci_dev *pdev, > } > pr_debug("Scatter list size %d\n", req->out_cnt); > for (i =3D 0; i < req->out_cnt; i++) { > - pr_debug("Buffer %d size %d, vptr 0x%p, dmaptr 0x%p\n", i= , > + pr_debug("Buffer %d size %d, vptr 0x%p, dmaptr 0x%llx\n", > i, > req->out[i].size, req->out[i].vptr, > - (void *) req->out[i].dma_addr); > + req->out[i].dma_addr); > pr_debug("Buffer hexdump (%d bytes)\n", req->out[i].size)= ; > print_hex_dump_debug("", DUMP_PREFIX_NONE, 16, 1, > req->out[i].vptr, req->out[i].size, > false); > @@ -84,149 +81,6 @@ static inline void free_pentry(struct > otx2_cpt_pending_entry *pentry) > pentry->busy =3D false; > } > > -static inline int setup_sgio_components(struct pci_dev *pdev, > - struct otx2_cpt_buf_ptr *list, > - int buf_count, u8 *buffer) > -{ > - struct otx2_cpt_sglist_component *sg_ptr =3D NULL; > - int ret =3D 0, i, j; > - int components; > - > - if (unlikely(!list)) { > - dev_err(&pdev->dev, "Input list pointer is NULL\n"); > - return -EFAULT; > - } > - > - for (i =3D 0; i < buf_count; i++) { > - if (unlikely(!list[i].vptr)) > - continue; > - list[i].dma_addr =3D dma_map_single(&pdev->dev, list[i].v= ptr, > - list[i].size, > - DMA_BIDIRECTIONAL); > - if (unlikely(dma_mapping_error(&pdev->dev, > list[i].dma_addr))) { > - dev_err(&pdev->dev, "Dma mapping failed\n"); > - ret =3D -EIO; > - goto sg_cleanup; > - } > - } > - components =3D buf_count / 4; > - sg_ptr =3D (struct otx2_cpt_sglist_component *)buffer; > - for (i =3D 0; i < components; i++) { > - sg_ptr->len0 =3D cpu_to_be16(list[i * 4 + 0].size); > - sg_ptr->len1 =3D cpu_to_be16(list[i * 4 + 1].size); > - sg_ptr->len2 =3D cpu_to_be16(list[i * 4 + 2].size); > - sg_ptr->len3 =3D cpu_to_be16(list[i * 4 + 3].size); > - sg_ptr->ptr0 =3D cpu_to_be64(list[i * 4 + 0].dma_addr); > - sg_ptr->ptr1 =3D cpu_to_be64(list[i * 4 + 1].dma_addr); > - sg_ptr->ptr2 =3D cpu_to_be64(list[i * 4 + 2].dma_addr); > - sg_ptr->ptr3 =3D cpu_to_be64(list[i * 4 + 3].dma_addr); > - sg_ptr++; > - } > - components =3D buf_count % 4; > - > - switch (components) { > - case 3: > - sg_ptr->len2 =3D cpu_to_be16(list[i * 4 + 2].size); > - sg_ptr->ptr2 =3D cpu_to_be64(list[i * 4 + 2].dma_addr); > - fallthrough; > - case 2: > - sg_ptr->len1 =3D cpu_to_be16(list[i * 4 + 1].size); > - sg_ptr->ptr1 =3D cpu_to_be64(list[i * 4 + 1].dma_addr); > - fallthrough; > - case 1: > - sg_ptr->len0 =3D cpu_to_be16(list[i * 4 + 0].size); > - sg_ptr->ptr0 =3D cpu_to_be64(list[i * 4 + 0].dma_addr); > - break; > - default: > - break; > - } > - return ret; > - > -sg_cleanup: > - for (j =3D 0; j < i; j++) { > - if (list[j].dma_addr) { > - dma_unmap_single(&pdev->dev, list[j].dma_addr, > - list[j].size, DMA_BIDIRECTIONAL)= ; > - } > - > - list[j].dma_addr =3D 0; > - } > - return ret; > -} > - > -static inline struct otx2_cpt_inst_info *info_create(struct pci_dev *pde= v, > - struct otx2_cpt_req_info > *req, > - gfp_t gfp) > -{ > - int align =3D OTX2_CPT_DMA_MINALIGN; > - struct otx2_cpt_inst_info *info; > - u32 dlen, align_dlen, info_len; > - u16 g_sz_bytes, s_sz_bytes; > - u32 total_mem_len; > - > - if (unlikely(req->in_cnt > OTX2_CPT_MAX_SG_IN_CNT || > - req->out_cnt > OTX2_CPT_MAX_SG_OUT_CNT)) { > - dev_err(&pdev->dev, "Error too many sg components\n"); > - return NULL; > - } > - > - g_sz_bytes =3D ((req->in_cnt + 3) / 4) * > - sizeof(struct otx2_cpt_sglist_component); > - s_sz_bytes =3D ((req->out_cnt + 3) / 4) * > - sizeof(struct otx2_cpt_sglist_component); > - > - dlen =3D g_sz_bytes + s_sz_bytes + SG_LIST_HDR_SIZE; > - align_dlen =3D ALIGN(dlen, align); > - info_len =3D ALIGN(sizeof(*info), align); > - total_mem_len =3D align_dlen + info_len + sizeof(union > otx2_cpt_res_s); > - > - info =3D kzalloc(total_mem_len, gfp); > - if (unlikely(!info)) > - return NULL; > - > - info->dlen =3D dlen; > - info->in_buffer =3D (u8 *)info + info_len; > - > - ((u16 *)info->in_buffer)[0] =3D req->out_cnt; > - ((u16 *)info->in_buffer)[1] =3D req->in_cnt; > - ((u16 *)info->in_buffer)[2] =3D 0; > - ((u16 *)info->in_buffer)[3] =3D 0; > - cpu_to_be64s((u64 *)info->in_buffer); > - > - /* Setup gather (input) components */ > - if (setup_sgio_components(pdev, req->in, req->in_cnt, > - &info->in_buffer[8])) { > - dev_err(&pdev->dev, "Failed to setup gather list\n"); > - goto destroy_info; > - } > - > - if (setup_sgio_components(pdev, req->out, req->out_cnt, > - &info->in_buffer[8 + g_sz_bytes])) { > - dev_err(&pdev->dev, "Failed to setup scatter list\n"); > - goto destroy_info; > - } > - > - info->dma_len =3D total_mem_len - info_len; > - info->dptr_baddr =3D dma_map_single(&pdev->dev, info->in_buffer, > - info->dma_len, > DMA_BIDIRECTIONAL); > - if (unlikely(dma_mapping_error(&pdev->dev, info->dptr_baddr))) { > - dev_err(&pdev->dev, "DMA Mapping failed for cpt req\n"); > - goto destroy_info; > - } > - /* > - * Get buffer for union otx2_cpt_res_s response > - * structure and its physical address > - */ > - info->completion_addr =3D info->in_buffer + align_dlen; > - info->comp_baddr =3D info->dptr_baddr + align_dlen; > - > - return info; > - > -destroy_info: > - otx2_cpt_info_destroy(pdev, info); > - return NULL; > -} > - > static int process_request(struct pci_dev *pdev, struct otx2_cpt_req_inf= o > *req, > struct otx2_cpt_pending_queue *pqueue, > struct otx2_cptlf_info *lf) > @@ -247,7 +101,7 @@ static int process_request(struct pci_dev *pdev, > struct otx2_cpt_req_info *req, > if (unlikely(!otx2_cptlf_started(lf->lfs))) > return -ENODEV; > > - info =3D info_create(pdev, req, gfp); > + info =3D lf->lfs->ops->cpt_sg_info_create(pdev, req, gfp); > if (unlikely(!info)) { > dev_err(&pdev->dev, "Setting up cpt inst info failed"); > return -ENOMEM; > @@ -303,8 +157,8 @@ static int process_request(struct pci_dev *pdev, > struct otx2_cpt_req_info *req, > > /* 64-bit swap for microcode data reads, not needed for addresses= */ > cpu_to_be64s(&iq_cmd.cmd.u); > - iq_cmd.dptr =3D info->dptr_baddr; > - iq_cmd.rptr =3D 0; > + iq_cmd.dptr =3D info->dptr_baddr | info->gthr_sz << 60; > + iq_cmd.rptr =3D info->rptr_baddr | info->sctr_sz << 60; > iq_cmd.cptr.u =3D 0; > iq_cmd.cptr.s.grp =3D ctrl->s.grp; > > -- > 2.25.1 > > > --=20 Regards, Kalesh A P --00000000000038e9b0060c377f60 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi=C2=A0Srujana,

Looks like = you ignored my comments on V1 of your patch.

On Mon, Dec 11, 2023 at 12:50= =E2=80=AFPM Srujana Challa <schalla@marvell.com> wrote:
Scatter Gather input format for CPT has ch= anged on CN10KB/CN10KA B0 HW
to make it comapatible with NIX Scatter Gather format to support SG mode for inline IPsec. This patch modifies the code to make the driver works
for the same. This patch also enables CPT firmware load for these chips.
Signed-off-by: Srujana Challa <schalla@marvell.com>
---
=C2=A0drivers/crypto/marvell/octeontx2/cn10k_cpt.c=C2=A0 |=C2=A0 19 +-
=C2=A0drivers/crypto/marvell/octeontx2/cn10k_cpt.h=C2=A0 |=C2=A0 =C2=A01 +<= br> =C2=A0.../marvell/octeontx2/otx2_cpt_common.h=C2=A0 =C2=A0 =C2=A0 =C2=A0|= =C2=A0 41 ++-
=C2=A0.../marvell/octeontx2/otx2_cpt_hw_types.h=C2=A0 =C2=A0 =C2=A0|=C2=A0 = =C2=A03 +
=C2=A0.../marvell/octeontx2/otx2_cpt_reqmgr.h=C2=A0 =C2=A0 =C2=A0 =C2=A0| 2= 93 ++++++++++++++++++
=C2=A0drivers/crypto/marvell/octeontx2/otx2_cptlf.h |=C2=A0 =C2=A02 +
=C2=A0.../marvell/octeontx2/otx2_cptpf_main.c=C2=A0 =C2=A0 =C2=A0 =C2=A0|= =C2=A0 26 +-
=C2=A0.../marvell/octeontx2/otx2_cptpf_mbox.c=C2=A0 =C2=A0 =C2=A0 =C2=A0|= =C2=A0 =C2=A02 +-
=C2=A0.../marvell/octeontx2/otx2_cptpf_ucode.c=C2=A0 =C2=A0 =C2=A0 |=C2=A0 = 33 +-
=C2=A0.../marvell/octeontx2/otx2_cptpf_ucode.h=C2=A0 =C2=A0 =C2=A0 |=C2=A0 = =C2=A03 +-
=C2=A0drivers/crypto/marvell/octeontx2/otx2_cptvf.h |=C2=A0 =C2=A02 +
=C2=A0.../marvell/octeontx2/otx2_cptvf_main.c=C2=A0 =C2=A0 =C2=A0 =C2=A0|= =C2=A0 13 +
=C2=A0.../marvell/octeontx2/otx2_cptvf_mbox.c=C2=A0 =C2=A0 =C2=A0 =C2=A0|= =C2=A0 26 ++
=C2=A0.../marvell/octeontx2/otx2_cptvf_reqmgr.c=C2=A0 =C2=A0 =C2=A0| 160 +-= --------
=C2=A014 files changed, 447 insertions(+), 177 deletions(-)

diff --git a/drivers/crypto/marvell/octeontx2/cn10k_cpt.c b/drivers/crypto/= marvell/octeontx2/cn10k_cpt.c
index 93d22b328991..b23ae3a020e0 100644
--- a/drivers/crypto/marvell/octeontx2/cn10k_cpt.c
+++ b/drivers/crypto/marvell/octeontx2/cn10k_cpt.c
@@ -14,12 +14,14 @@ static struct cpt_hw_ops otx2_hw_ops =3D {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 .send_cmd =3D otx2_cpt_send_cmd,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 .cpt_get_compcode =3D otx2_cpt_get_compcode, =C2=A0 =C2=A0 =C2=A0 =C2=A0 .cpt_get_uc_compcode =3D otx2_cpt_get_uc_compco= de,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0.cpt_sg_info_create =3D otx2_sg_info_create, =C2=A0};

=C2=A0static struct cpt_hw_ops cn10k_hw_ops =3D {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 .send_cmd =3D cn10k_cpt_send_cmd,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 .cpt_get_compcode =3D cn10k_cpt_get_compcode, =C2=A0 =C2=A0 =C2=A0 =C2=A0 .cpt_get_uc_compcode =3D cn10k_cpt_get_uc_compc= ode,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0.cpt_sg_info_create =3D otx2_sg_info_create, =C2=A0};

=C2=A0static void cn10k_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, u32 in= sts_num,
@@ -78,12 +80,9 @@ int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf)=
=C2=A0 =C2=A0 =C2=A0 =C2=A0 struct pci_dev *pdev =3D cptvf->pdev;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 resource_size_t offset, size;

-=C2=A0 =C2=A0 =C2=A0 =C2=A0if (!test_bit(CN10K_LMTST, &cptvf->cap_f= lag)) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cptvf->lfs.ops = =3D &otx2_hw_ops;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (!test_bit(CN10K_LMTST, &cptvf->cap_f= lag))
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return 0;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0}

-=C2=A0 =C2=A0 =C2=A0 =C2=A0cptvf->lfs.ops =3D &cn10k_hw_ops;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 offset =3D pci_resource_start(pdev, PCI_MBOX_BA= R_NUM);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 size =3D pci_resource_len(pdev, PCI_MBOX_BAR_NU= M);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Map VF LMILINE region */
@@ -96,3 +95,15 @@ int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf)=
=C2=A0 =C2=A0 =C2=A0 =C2=A0 return 0;
=C2=A0}
=C2=A0EXPORT_SYMBOL_NS_GPL(cn10k_cptvf_lmtst_init, CRYPTO_DEV_OCTEONTX2_CPT= );
+
+int cptvf_hw_ops_get(struct otx2_cptvf_dev *cptvf)
+{
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (!test_bit(CN10K_LMTST, &cptvf->cap_f= lag)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cptvf->lfs.ops = =3D &otx2_hw_ops;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+=C2=A0 =C2=A0 =C2=A0 =C2=A0cptvf->lfs.ops =3D &cn10k_hw_ops;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;
+}
+EXPORT_SYMBOL_NS_GPL(cptvf_hw_ops_get, CRYPTO_DEV_OCTEONTX2_CPT);
[Kalesh]: You can make this function return void as it returns= 0 always.
+void cptvf_hw_ops_get(struct otx2_cptvf_dev *cptvf)+{
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (!test_bit(CN10K_LMTST, &= amp;cptvf->cap_flag))
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0cptvf->lfs.ops =3D &otx2_hw_ops;
+=C2=A0 =C2=A0 =C2=A0 = =C2=A0else
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cptvf= ->lfs.ops =3D &cn10k_hw_ops;
+}
diff --git a/drivers/crypto/marvell/octeontx2/cn10k_cpt.h b/drivers/crypto/= marvell/octeontx2/cn10k_cpt.h
index aaefc7e38e06..0f714ee564f5 100644
--- a/drivers/crypto/marvell/octeontx2/cn10k_cpt.h
+++ b/drivers/crypto/marvell/octeontx2/cn10k_cpt.h
@@ -30,5 +30,6 @@ static inline u8 otx2_cpt_get_uc_compcode(union otx2_cpt_= res_s *result)

=C2=A0int cn10k_cptpf_lmtst_init(struct otx2_cptpf_dev *cptpf);
=C2=A0int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf);
+int cptvf_hw_ops_get(struct otx2_cptvf_dev *cptvf);

=C2=A0#endif /* __CN10K_CPTLF_H */
diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h b/drivers/c= rypto/marvell/octeontx2/otx2_cpt_common.h
index 46b778bbbee4..2a7544252444 100644
--- a/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h
+++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h
@@ -102,7 +102,10 @@ union otx2_cpt_eng_caps {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 u64 kasumi:1;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 u64 des:1;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 u64 crc:1;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0u64 reserved_14_63:= 50;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0u64 mmul:1;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0u64 reserved_15_33:= 19;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0u64 pdcp_chain:1; +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0u64 reserved_35_63:= 29;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 };
=C2=A0};

@@ -145,6 +148,41 @@ static inline bool is_dev_otx2(struct pci_dev *pdev) =C2=A0 =C2=A0 =C2=A0 =C2=A0 return false;
=C2=A0}

+static inline bool is_dev_cn10ka(struct pci_dev *pdev)
+{
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (pdev->subsystem_device =3D=3D CPT_PCI_SU= BSYS_DEVID_CN10K_A)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return true;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return false;
+}
[Kalesh]: You can further simply this as:
return pdev->subsystem_device =3D=3D CPT_PCI_SUBSYS_DEVID_CN10K_A=C2=A0=
+
+static inline bool is_dev_cn10ka_ax(struct pci_dev *pdev)
+{
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (pdev->subsystem_device =3D=3D CPT_PCI_SU= BSYS_DEVID_CN10K_A &&
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0((pdev->revision & 0xFF) = =3D=3D 4 || (pdev->revision & 0xFF) =3D=3D 0x50 ||
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (pdev->revision & 0xff) = =3D=3D 0x51))
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return true;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return false;
+}
+
+static inline bool is_dev_cn10kb(struct pci_dev *pdev)
+{
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (pdev->subsystem_device =3D=3D CPT_PCI_SU= BSYS_DEVID_CN10K_B)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return true;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return false;
+}
[Kalesh]: You can further simply this as:
return pdev->subsystem_device =3D=3D CPT_PCI_SUBSYS_DEVID_CN10K_B=C2=A0=
+
+static inline bool is_dev_cn10ka_b0(struct pci_dev *pdev)
+{
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (pdev->subsystem_device =3D=3D CPT_PCI_SU= BSYS_DEVID_CN10K_A &&
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(pdev->revision & 0xFF) = =3D=3D 0x54)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return true;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return false;
+}
+
=C2=A0static inline void otx2_cpt_set_hw_caps(struct pci_dev *pdev,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 unsigned= long *cap_flag)
=C2=A0{
@@ -154,7 +192,6 @@ static inline void otx2_cpt_set_hw_caps(struct pci_dev = *pdev,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
=C2=A0}

-
[Kalesh]: This change looks unrelated=C2=A0
=C2=A0int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *p= dev);
=C2=A0int otx2_cpt_send_mbox_msg(struct otx2_mbox *mbox, struct pci_dev *pd= ev);

diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h b/drivers= /crypto/marvell/octeontx2/otx2_cpt_hw_types.h
index 6f947978e4e8..756aee0c2b05 100644
--- a/drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h
+++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h
@@ -13,6 +13,9 @@
=C2=A0#define CN10K_CPT_PCI_PF_DEVICE_ID 0xA0F2
=C2=A0#define CN10K_CPT_PCI_VF_DEVICE_ID 0xA0F3

+#define CPT_PCI_SUBSYS_DEVID_CN10K_A 0xB900
+#define CPT_PCI_SUBSYS_DEVID_CN10K_B 0xBD00
+
=C2=A0/* Mailbox interrupts offset */
=C2=A0#define OTX2_CPT_PF_MBOX_INT=C2=A0 =C2=A06
=C2=A0#define OTX2_CPT_PF_INT_VEC_E_MBOXX(x, a) ((x) + (a))
diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h b/drivers/c= rypto/marvell/octeontx2/otx2_cpt_reqmgr.h
index dbb1ee746f4c..b0f426531a42 100644
--- a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h
+++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h
@@ -143,6 +143,8 @@ struct otx2_cpt_inst_info {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 unsigned long time_in;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 u32 dlen;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 u32 dma_len;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0u64 gthr_sz;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0u64 sctr_sz;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 u8 extra_time;
=C2=A0};

@@ -157,6 +159,16 @@ struct otx2_cpt_sglist_component {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 __be64 ptr3;
=C2=A0};

+struct cn10kb_cpt_sglist_component {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0u16 len0;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0u16 len1;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0u16 len2;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0u16 valid_segs;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0u64 ptr0;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0u64 ptr1;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0u64 ptr2;
+};
+
=C2=A0static inline void otx2_cpt_info_destroy(struct pci_dev *pdev,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0st= ruct otx2_cpt_inst_info *info)
=C2=A0{
@@ -188,6 +200,287 @@ static inline void otx2_cpt_info_destroy(struct pci_d= ev *pdev,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 kfree(info);
=C2=A0}

+static inline int setup_sgio_components(struct pci_dev *pdev,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0struct ot= x2_cpt_buf_ptr *list,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0int buf_c= ount, u8 *buffer)
+{
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct otx2_cpt_sglist_component *sg_ptr =3D NU= LL;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0int ret =3D 0, i, j;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0int components;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (unlikely(!list)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev_err(&pdev-&= gt;dev, "Input list pointer is NULL\n");
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return -EFAULT;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i < buf_count; i++) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (unlikely(!list[= i].vptr))
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0continue;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0list[i].dma_addr = =3D dma_map_single(&pdev->dev, list[i].vptr,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0list[i].size,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0DMA_BIDIRECTIONAL);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (unlikely(dma_ma= pping_error(&pdev->dev, list[i].dma_addr))) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0dev_err(&pdev->dev, "Dma mapping failed\n");
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0ret =3D -EIO;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0goto sg_cleanup;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+=C2=A0 =C2=A0 =C2=A0 =C2=A0components =3D buf_count / 4;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr =3D (struct otx2_cpt_sglist_component *)= buffer;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i < components; i++) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->len0 =3D= cpu_to_be16(list[i * 4 + 0].size);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->len1 =3D= cpu_to_be16(list[i * 4 + 1].size);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->len2 =3D= cpu_to_be16(list[i * 4 + 2].size);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->len3 =3D= cpu_to_be16(list[i * 4 + 3].size);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->ptr0 =3D= cpu_to_be64(list[i * 4 + 0].dma_addr);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->ptr1 =3D= cpu_to_be64(list[i * 4 + 1].dma_addr);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->ptr2 =3D= cpu_to_be64(list[i * 4 + 2].dma_addr);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->ptr3 =3D= cpu_to_be64(list[i * 4 + 3].dma_addr);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr++;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+=C2=A0 =C2=A0 =C2=A0 =C2=A0components =3D buf_count % 4;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0switch (components) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0case 3:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->len2 =3D= cpu_to_be16(list[i * 4 + 2].size);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->ptr2 =3D= cpu_to_be64(list[i * 4 + 2].dma_addr);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0fallthrough;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0case 2:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->len1 =3D= cpu_to_be16(list[i * 4 + 1].size);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->ptr1 =3D= cpu_to_be64(list[i * 4 + 1].dma_addr);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0fallthrough;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0case 1:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->len0 =3D= cpu_to_be16(list[i * 4 + 0].size);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->ptr0 =3D= cpu_to_be64(list[i * 4 + 0].dma_addr);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0default:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return ret;
+
+sg_cleanup:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0for (j =3D 0; j < i; j++) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (list[j].dma_add= r) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0dma_unmap_single(&pdev->dev, list[j].dma_addr,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 list[j].= size, DMA_BIDIRECTIONAL);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0list[j].dma_addr = =3D 0;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return ret;
+}
+
+static inline int sgv2io_components_setup(struct pci_dev *pdev,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0st= ruct otx2_cpt_buf_ptr *list,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0in= t buf_count, u8 *buffer)
+{
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct cn10kb_cpt_sglist_component *sg_ptr =3D = NULL;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0int ret =3D 0, i, j;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0int components;
[Kalesh]: = maintain RCT order=C2=A0
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (unlikely(!list)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev_err(&pdev-&= gt;dev, "Input list pointer is NULL\n");
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return -EFAULT;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i < buf_count; i++) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (unlikely(!list[= i].vptr))
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0continue;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0list[i].dma_addr = =3D dma_map_single(&pdev->dev, list[i].vptr,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0list[i].size,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0DMA_BIDIRECTIONAL);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (unlikely(dma_ma= pping_error(&pdev->dev, list[i].dma_addr))) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0dev_err(&pdev->dev, "Dma mapping failed\n");
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0ret =3D -EIO;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0goto sg_cleanup;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+=C2=A0 =C2=A0 =C2=A0 =C2=A0components =3D buf_count / 3;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr =3D (struct cn10kb_cpt_sglist_component = *)buffer;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i < components; i++) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->len0 =3D= list[i * 3 + 0].size;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->len1 =3D= list[i * 3 + 1].size;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->len2 =3D= list[i * 3 + 2].size;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->ptr0 =3D= list[i * 3 + 0].dma_addr;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->ptr1 =3D= list[i * 3 + 1].dma_addr;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->ptr2 =3D= list[i * 3 + 2].dma_addr;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->valid_se= gs =3D 3;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr++;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+=C2=A0 =C2=A0 =C2=A0 =C2=A0components =3D buf_count % 3;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->valid_segs =3D components;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0switch (components) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0case 2:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->len1 =3D= list[i * 3 + 1].size;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->ptr1 =3D= list[i * 3 + 1].dma_addr;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0fallthrough;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0case 1:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->len0 =3D= list[i * 3 + 0].size;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->ptr0 =3D= list[i * 3 + 0].dma_addr;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0default:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return ret;
+
+sg_cleanup:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0for (j =3D 0; j < i; j++) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (list[j].dma_add= r) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0dma_unmap_single(&pdev->dev, list[j].dma_addr,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 list[j].= size, DMA_BIDIRECTIONAL);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0list[j].dma_addr = =3D 0;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return ret;
+}
+
+static inline struct otx2_cpt_inst_info *cn10k_sgv2_info_create(
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0struct pci_dev *pdev,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0struct otx2_cpt_req_info *req,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0gfp_t gfp)
+{
+=C2=A0 =C2=A0 =C2=A0 =C2=A0u32 dlen =3D 0, g_len, sg_len, info_len;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0int align =3D OTX2_CPT_DMA_MINALIGN;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct otx2_cpt_inst_info *info;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0u16 g_sz_bytes, s_sz_bytes;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0u32 total_mem_len;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0int i;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0g_sz_bytes =3D ((req->in_cnt + 2) / 3) *
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0sizeof(struct cn10kb_cpt_sglist_component);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0s_sz_bytes =3D ((req->out_cnt + 2) / 3) * +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0sizeof(struct cn10kb_cpt_sglist_component);
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0g_len =3D ALIGN(g_sz_bytes, align);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0sg_len =3D ALIGN(g_len + s_sz_bytes, align); +=C2=A0 =C2=A0 =C2=A0 =C2=A0info_len =3D ALIGN(sizeof(*info), align);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0total_mem_len =3D sg_len + info_len + sizeof(un= ion otx2_cpt_res_s);
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0info =3D kzalloc(total_mem_len, gfp);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (unlikely(!info))
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return NULL;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i < req->in_cnt; i++)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dlen +=3D req->i= n[i].size;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0info->dlen =3D dlen;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0info->in_buffer =3D (u8 *)info + info_len; +=C2=A0 =C2=A0 =C2=A0 =C2=A0info->gthr_sz =3D req->in_cnt;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0info->sctr_sz =3D req->out_cnt;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Setup gather (input) components */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (sgv2io_components_setup(pdev, req->in, r= eq->in_cnt,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0info->in_buffer)) {<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev_err(&pdev-&= gt;dev, "Failed to setup gather list\n");
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto destroy_info;<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (sgv2io_components_setup(pdev, req->out, = req->out_cnt,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&info->in_buffer= [g_len])) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev_err(&pdev-&= gt;dev, "Failed to setup scatter list\n");
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto destroy_info;<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0info->dma_len =3D total_mem_len - info_len;<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0info->dptr_baddr =3D dma_map_single(&pde= v->dev, info->in_buffer,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0in= fo->dma_len, DMA_BIDIRECTIONAL);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (unlikely(dma_mapping_error(&pdev->de= v, info->dptr_baddr))) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev_err(&pdev-&= gt;dev, "DMA Mapping failed for cpt req\n");
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto destroy_info;<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+=C2=A0 =C2=A0 =C2=A0 =C2=A0info->rptr_baddr =3D info->dptr_baddr + g= _len;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0/*
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 * Get buffer for union otx2_cpt_res_s response=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 * structure and its physical address
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0info->completion_addr =3D info->in_buffer= + sg_len;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0info->comp_baddr =3D info->dptr_baddr + s= g_len;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return info;
+
+destroy_info:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0otx2_cpt_info_destroy(pdev, info);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return NULL;
+}
+
+/* SG list header size in bytes */
+#define SG_LIST_HDR_SIZE=C2=A0 =C2=A0 =C2=A0 =C2=A08
+static inline struct otx2_cpt_inst_info *otx2_sg_info_create(
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0struct pci_dev *pdev,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0struct otx2_cpt_req_info *req,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0gfp_t gfp)
+{
+=C2=A0 =C2=A0 =C2=A0 =C2=A0int align =3D OTX2_CPT_DMA_MINALIGN;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct otx2_cpt_inst_info *info;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0u32 dlen, align_dlen, info_len;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0u16 g_sz_bytes, s_sz_bytes;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0u32 total_mem_len;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (unlikely(req->in_cnt > OTX2_CPT_MAX_S= G_IN_CNT ||
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 req-= >out_cnt > OTX2_CPT_MAX_SG_OUT_CNT)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev_err(&pdev-&= gt;dev, "Error too many sg components\n");
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return NULL;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0g_sz_bytes =3D ((req->in_cnt + 3) / 4) *
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0sizeof(struct otx2_cpt_sglist_component);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0s_sz_bytes =3D ((req->out_cnt + 3) / 4) * +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0sizeof(struct otx2_cpt_sglist_component);
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0dlen =3D g_sz_bytes + s_sz_bytes + SG_LIST_HDR_= SIZE;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0align_dlen =3D ALIGN(dlen, align);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0info_len =3D ALIGN(sizeof(*info), align);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0total_mem_len =3D align_dlen + info_len + sizeo= f(union otx2_cpt_res_s);
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0info =3D kzalloc(total_mem_len, gfp);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (unlikely(!info))
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return NULL;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0info->dlen =3D dlen;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0info->in_buffer =3D (u8 *)info + info_len; +
+=C2=A0 =C2=A0 =C2=A0 =C2=A0((u16 *)info->in_buffer)[0] =3D req->out_= cnt;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0((u16 *)info->in_buffer)[1] =3D req->in_c= nt;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0((u16 *)info->in_buffer)[2] =3D 0;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0((u16 *)info->in_buffer)[3] =3D 0;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_to_be64s((u64 *)info->in_buffer);
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Setup gather (input) components */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (setup_sgio_components(pdev, req->in, req= ->in_cnt,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&info->in_buffer[8])) {=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev_err(&pdev-&= gt;dev, "Failed to setup gather list\n");
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto destroy_info;<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (setup_sgio_components(pdev, req->out, re= q->out_cnt,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&info->in_buffer[8 + g_= sz_bytes])) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev_err(&pdev-&= gt;dev, "Failed to setup scatter list\n");
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto destroy_info;<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0info->dma_len =3D total_mem_len - info_len;<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0info->dptr_baddr =3D dma_map_single(&pde= v->dev, info->in_buffer,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0in= fo->dma_len, DMA_BIDIRECTIONAL);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (unlikely(dma_mapping_error(&pdev->de= v, info->dptr_baddr))) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev_err(&pdev-&= gt;dev, "DMA Mapping failed for cpt req\n");
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto destroy_info;<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+=C2=A0 =C2=A0 =C2=A0 =C2=A0/*
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 * Get buffer for union otx2_cpt_res_s response=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 * structure and its physical address
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0info->completion_addr =3D info->in_buffer= + align_dlen;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0info->comp_baddr =3D info->dptr_baddr + a= lign_dlen;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return info;
+
+destroy_info:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0otx2_cpt_info_destroy(pdev, info);
[Kalesh]" Where is the memory allocated for "info" = getting freed. The memory is allocated locally inside this function.
<= blockquote class=3D"gmail_quote" style=3D"margin:0px 0px 0px 0.8ex;border-l= eft:1px solid rgb(204,204,204);padding-left:1ex"> +=C2=A0 =C2=A0 =C2=A0 =C2=A0return NULL;
+}
+
=C2=A0struct otx2_cptlf_wqe;
=C2=A0int otx2_cpt_do_request(struct pci_dev *pdev, struct otx2_cpt_req_inf= o *req,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 int cpu_num);
diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptlf.h b/drivers/crypto= /marvell/octeontx2/otx2_cptlf.h
index 5302fe3d0e6f..70138d65ba9e 100644
--- a/drivers/crypto/marvell/octeontx2/otx2_cptlf.h
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptlf.h
@@ -99,6 +99,8 @@ struct cpt_hw_ops {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0struct otx2_cptlf_info *lf);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 u8 (*cpt_get_compcode)(union otx2_cpt_res_s *re= sult);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 u8 (*cpt_get_uc_compcode)(union otx2_cpt_res_s = *result);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct otx2_cpt_inst_info * (*cpt_sg_info_creat= e)(struct pci_dev *pdev,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 struct otx2_cpt_req_in= fo *req, gfp_t gfp);
=C2=A0};

=C2=A0struct otx2_cptlfs_info {
diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c b/drivers/c= rypto/marvell/octeontx2/otx2_cptpf_main.c
index 5436b0d3685c..c64c50a964ed 100644
--- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
@@ -14,6 +14,8 @@
=C2=A0#define OTX2_CPT_DRV_STRING=C2=A0 "Marvell RVU CPT Physical Func= tion Driver"

=C2=A0#define CPT_UC_RID_CN9K_B0=C2=A0 =C2=A01
+#define CPT_UC_RID_CN10K_A=C2=A0 =C2=A04
+#define CPT_UC_RID_CN10K_B=C2=A0 =C2=A05

=C2=A0static void cptpf_enable_vfpf_mbox_intr(struct otx2_cptpf_dev *cptpf,=
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int num_= vfs)
@@ -587,6 +589,26 @@ static int cpt_is_pf_usable(struct otx2_cptpf_dev *cpt= pf)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 return 0;
=C2=A0}

+static int cptpf_get_rid(struct pci_dev *pdev, struct otx2_cptpf_dev *cptp= f)
+{
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct otx2_cpt_eng_grps *eng_grps =3D &cpt= pf->eng_grps;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0u64 reg_val =3D 0x0;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (is_dev_otx2(pdev)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0eng_grps->rid = =3D pdev->revision;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+=C2=A0 =C2=A0 =C2=A0 =C2=A0otx2_cpt_read_af_reg(&cptpf->afpf_mbox, = pdev, CPT_AF_CTL, &reg_val,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 BLKADDR_CPT0);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if ((is_dev_cn10ka_b0(pdev) && (reg_val= & BIT_ULL(18))) ||
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0is_dev_cn10ka_ax(pdev))
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0eng_grps->rid = =3D CPT_UC_RID_CN10K_A;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0else if (is_dev_cn10kb(pdev) || is_dev_cn10ka_b= 0(pdev))
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0eng_grps->rid = =3D CPT_UC_RID_CN10K_B;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;
+}
[Kalesh]: You can convert this function to return v= oid as it always returns 0 always.
+
=C2=A0static void cptpf_check_block_implemented(struct otx2_cptpf_dev *cptp= f)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0 =C2=A0 u64 cfg;
@@ -657,7 +679,9 @@ static int cptpf_sriov_enable(struct pci_dev *pdev, int= num_vfs)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 ret =3D cptpf_register_vfpf_intr(cptpf, num_vfs= );
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (ret)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto destroy_flr; -
+=C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D cptpf_get_rid(pdev, cptpf);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (ret)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto disable_intr;<= br> =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Get CPT HW capabilities using LOAD_FVC opera= tion. */
=C2=A0 =C2=A0 =C2=A0 =C2=A0 ret =3D otx2_cpt_discover_eng_capabilities(cptp= f);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (ret)
diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c b/drivers/c= rypto/marvell/octeontx2/otx2_cptpf_mbox.c
index 480b3720f15a..390ed146d309 100644
--- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_mbox.c
@@ -78,7 +78,7 @@ static int handle_msg_get_caps(struct otx2_cptpf_dev *cpt= pf,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 rsp->hdr.sig =3D OTX2_MBOX_RSP_SIG;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 rsp->hdr.pcifunc =3D req->pcifunc;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 rsp->cpt_pf_drv_version =3D OTX2_CPT_PF_DRV_= VERSION;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0rsp->cpt_revision =3D cptpf->pdev->rev= ision;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0rsp->cpt_revision =3D cptpf->eng_grps.rid= ;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 memcpy(&rsp->eng_caps, &cptpf->en= g_caps, sizeof(rsp->eng_caps));

=C2=A0 =C2=A0 =C2=A0 =C2=A0 return 0;
diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c b/drivers/= crypto/marvell/octeontx2/otx2_cptpf_ucode.c
index 1958b797a421..7fccc348f66e 100644
--- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
@@ -117,12 +117,10 @@ static char *get_ucode_type_str(int ucode_type)

=C2=A0static int get_ucode_type(struct device *dev,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 struct otx2_cpt_ucode_hdr *ucode_hdr,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0int *ucode_type)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0int *ucode_type, u16 rid)
=C2=A0{
-=C2=A0 =C2=A0 =C2=A0 =C2=A0struct otx2_cptpf_dev *cptpf =3D dev_get_drvdat= a(dev);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 char ver_str_prefix[OTX2_CPT_UCODE_VER_STR_SZ];=
=C2=A0 =C2=A0 =C2=A0 =C2=A0 char tmp_ver_str[OTX2_CPT_UCODE_VER_STR_SZ]; -=C2=A0 =C2=A0 =C2=A0 =C2=A0struct pci_dev *pdev =3D cptpf->pdev;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 int i, val =3D 0;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 u8 nn;

@@ -130,7 +128,7 @@ static int get_ucode_type(struct device *dev,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 for (i =3D 0; i < strlen(tmp_ver_str); i++)<= br> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 tmp_ver_str[i] =3D = tolower(tmp_ver_str[i]);

-=C2=A0 =C2=A0 =C2=A0 =C2=A0sprintf(ver_str_prefix, "ocpt-%02d", = pdev->revision);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0sprintf(ver_str_prefix, "ocpt-%02d", = rid);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (!strnstr(tmp_ver_str, ver_str_prefix, OTX2_= CPT_UCODE_VER_STR_SZ))
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return -EINVAL;

@@ -359,7 +357,7 @@ static int cpt_attach_and_enable_cores(struct otx2_cpt_= eng_grp_info *eng_grp,
=C2=A0}

=C2=A0static int load_fw(struct device *dev, struct fw_info_t *fw_info,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 char *filen= ame)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 char *filen= ame, u16 rid)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0 =C2=A0 struct otx2_cpt_ucode_hdr *ucode_hdr;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 struct otx2_cpt_uc_info_t *uc_info;
@@ -375,7 +373,7 @@ static int load_fw(struct device *dev, struct fw_info_t= *fw_info,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto free_uc_info;<= br>
=C2=A0 =C2=A0 =C2=A0 =C2=A0 ucode_hdr =3D (struct otx2_cpt_ucode_hdr *)uc_i= nfo->fw->data;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D get_ucode_type(dev, ucode_hdr, &uco= de_type);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D get_ucode_type(dev, ucode_hdr, &uco= de_type, rid);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (ret)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto release_fw;
@@ -389,6 +387,7 @@ static int load_fw(struct device *dev, struct fw_info_t= *fw_info,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 set_ucode_filename(&uc_info->ucode, file= name);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 memcpy(uc_info->ucode.ver_str, ucode_hdr->= ;ver_str,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0OTX2_CPT_UCODE_VER_S= TR_SZ);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0uc_info->ucode.ver_str[OTX2_CPT_UCODE_VER_ST= R_SZ] =3D 0;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 uc_info->ucode.ver_num =3D ucode_hdr->ver= _num;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 uc_info->ucode.type =3D ucode_type;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 uc_info->ucode.size =3D ucode_size;
@@ -448,7 +447,8 @@ static void print_uc_info(struct fw_info_t *fw_info) =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
=C2=A0}

-static int cpt_ucode_load_fw(struct pci_dev *pdev, struct fw_info_t *fw_in= fo)
+static int cpt_ucode_load_fw(struct pci_dev *pdev, struct fw_info_t *fw_in= fo,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 u16 rid)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0 =C2=A0 char filename[OTX2_CPT_NAME_LENGTH];
=C2=A0 =C2=A0 =C2=A0 =C2=A0 char eng_type[8] =3D {0};
@@ -462,9 +462,9 @@ static int cpt_ucode_load_fw(struct pci_dev *pdev, stru= ct fw_info_t *fw_info)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 eng_type[i] =3D tolower(eng_type[i]);

=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 snprintf(filename, = sizeof(filename), "mrvl/cpt%02d/%s.out",
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 pdev->revision, eng_type);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 rid, eng_type);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Request firmware= for each engine type */
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D load_fw(&am= p;pdev->dev, fw_info, filename);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D load_fw(&am= p;pdev->dev, fw_info, filename, rid);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (ret)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 goto release_fw;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
@@ -1155,7 +1155,7 @@ int otx2_cpt_create_eng_grps(struct otx2_cptpf_dev *c= ptpf,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (eng_grps->is_grps_created)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto unlock;

-=C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D cpt_ucode_load_fw(pdev, &fw_info);<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D cpt_ucode_load_fw(pdev, &fw_info, e= ng_grps->rid);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (ret)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto unlock;

@@ -1230,14 +1230,16 @@ int otx2_cpt_create_eng_grps(struct otx2_cptpf_dev = *cptpf,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
=C2=A0 =C2=A0 =C2=A0 =C2=A0 rnm_to_cpt_errata_fixup(&pdev->dev);

+=C2=A0 =C2=A0 =C2=A0 =C2=A0otx2_cpt_read_af_reg(&cptpf->afpf_mbox, = pdev, CPT_AF_CTL, &reg_val,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 BLKADDR_CPT0);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 /*
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* Configure engine group mask to allow co= ntext prefetching
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* for the groups and enable random number= request, to enable
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* CPT to request random numbers from RNM.=
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
+=C2=A0 =C2=A0 =C2=A0 =C2=A0reg_val |=3D OTX2_CPT_ALL_ENG_GRPS_MASK <<= ; 3 | BIT_ULL(16);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 otx2_cpt_write_af_reg(&cptpf->afpf_mbox,= pdev, CPT_AF_CTL,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0OTX2_CPT_ALL_ENG_GRPS_MASK << 3 | BIT_= ULL(16),
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0BLKADDR_CPT0);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0reg_val, BLKADDR_CPT0);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 /*
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* Set interval to periodically flush dirt= y data for the next
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0* CTX cache entry. Set the interval count= to maximum supported
@@ -1412,7 +1414,7 @@ static int create_eng_caps_discovery_grps(struct pci_= dev *pdev,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 int ret;

=C2=A0 =C2=A0 =C2=A0 =C2=A0 mutex_lock(&eng_grps->lock);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D cpt_ucode_load_fw(pdev, &fw_info);<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D cpt_ucode_load_fw(pdev, &fw_info, e= ng_grps->rid);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (ret) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 mutex_unlock(&e= ng_grps->lock);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return ret;
@@ -1686,13 +1688,14 @@ int otx2_cpt_dl_custom_egrp_create(struct otx2_cptp= f_dev *cptpf,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto err_unlock; =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
=C2=A0 =C2=A0 =C2=A0 =C2=A0 INIT_LIST_HEAD(&fw_info.ucodes);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D load_fw(dev, &fw_info, ucode_filena= me[0]);
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D load_fw(dev, &fw_info, ucode_filena= me[0], eng_grps->rid);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (ret) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(dev, "= Unable to load firmware %s\n", ucode_filename[0]);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto err_unlock; =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (ucode_idx > 1) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D load_fw(dev= , &fw_info, ucode_filename[1]);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D load_fw(dev= , &fw_info, ucode_filename[1], eng_grps->rid);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (ret) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 dev_err(dev, "Unable to load firmware %s\n",
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ucode_filename[1]);
diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h b/drivers/= crypto/marvell/octeontx2/otx2_cptpf_ucode.h
index e69320a54b5d..365fe8943bd9 100644
--- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.h
@@ -73,7 +73,7 @@ struct otx2_cpt_ucode_hdr {
=C2=A0};

=C2=A0struct otx2_cpt_ucode {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0u8 ver_str[OTX2_CPT_UCODE_VER_STR_SZ];/*
+=C2=A0 =C2=A0 =C2=A0 =C2=A0u8 ver_str[OTX2_CPT_UCODE_VER_STR_SZ + 1];/* =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0* ucode version in readable
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0* format
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0*/
@@ -150,6 +150,7 @@ struct otx2_cpt_eng_grps {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 int engs_num;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* total number of engines supported */<= br> =C2=A0 =C2=A0 =C2=A0 =C2=A0 u8 eng_ref_cnt[OTX2_CPT_MAX_ENGINES];/* engines= reference count */
=C2=A0 =C2=A0 =C2=A0 =C2=A0 bool is_grps_created; /* Is the engine groups a= re already created */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0u16 rid;
=C2=A0};
=C2=A0struct otx2_cptpf_dev;
=C2=A0int otx2_cpt_init_eng_grps(struct pci_dev *pdev,
diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf.h b/drivers/crypto= /marvell/octeontx2/otx2_cptvf.h
index 994291e90da1..11ab9af1df15 100644
--- a/drivers/crypto/marvell/octeontx2/otx2_cptvf.h
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptvf.h
@@ -22,6 +22,7 @@ struct otx2_cptvf_dev {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 int blkaddr;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 void *bbuf_base;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 unsigned long cap_flag;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0u64 eng_caps[OTX2_CPT_MAX_ENG_TYPES];
=C2=A0};

=C2=A0irqreturn_t otx2_cptvf_pfvf_mbox_intr(int irq, void *arg);
@@ -29,5 +30,6 @@ void otx2_cptvf_pfvf_mbox_handler(struct work_struct *wor= k);
=C2=A0int otx2_cptvf_send_eng_grp_num_msg(struct otx2_cptvf_dev *cptvf, int= eng_type);
=C2=A0int otx2_cptvf_send_kvf_limits_msg(struct otx2_cptvf_dev *cptvf);
=C2=A0int otx2_cpt_mbox_bbuf_init(struct otx2_cptvf_dev *cptvf, struct pci_= dev *pdev);
+int otx2_cptvf_send_caps_msg(struct otx2_cptvf_dev *cptvf);

=C2=A0#endif /* __OTX2_CPTVF_H */
diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c b/drivers/c= rypto/marvell/octeontx2/otx2_cptvf_main.c
index bac729c885f9..5d1e11135c17 100644
--- a/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c
@@ -380,6 +380,19 @@ static int otx2_cptvf_probe(struct pci_dev *pdev,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto destroy_pfvf_m= box;

=C2=A0 =C2=A0 =C2=A0 =C2=A0 cptvf->blkaddr =3D BLKADDR_CPT0;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D cptvf_hw_ops_get(cptvf);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (ret)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto unregister_int= errupts;
[Kalesh]: No need to check return value here.= See my other comment above.=C2=A0
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0ret =3D otx2_cptvf_send_caps_msg(cptvf);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (ret) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev_err(&pdev-&= gt;dev, "Couldn't get CPT engine capabilities.\n");
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto unregister_int= errupts;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (cptvf->eng_caps[OTX2_CPT_SE_TYPES] &= BIT_ULL(35))
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cptvf->lfs.ops-&= gt;cpt_sg_info_create =3D cn10k_sgv2_info_create;
+
=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Initialize CPT LFs */
=C2=A0 =C2=A0 =C2=A0 =C2=A0 ret =3D cptvf_lf_init(cptvf);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (ret)
diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c b/drivers/c= rypto/marvell/octeontx2/otx2_cptvf_mbox.c
index 75c403f2b1d9..f68da1d08fdf 100644
--- a/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c
@@ -72,6 +72,7 @@ static void process_pfvf_mbox_mbox_msg(struct otx2_cptvf_= dev *cptvf,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 struct otx2_cptlfs_info *lfs =3D &cptvf->= ;lfs;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 struct otx2_cpt_kvf_limits_rsp *rsp_limits;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 struct otx2_cpt_egrp_num_rsp *rsp_grp;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct otx2_cpt_caps_rsp *eng_caps;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 struct cpt_rd_wr_reg_msg *rsp_reg;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 struct msix_offset_rsp *rsp_msix;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 int i;
@@ -127,6 +128,11 @@ static void process_pfvf_mbox_mbox_msg(struct otx2_cpt= vf_dev *cptvf,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 rsp_limits =3D (str= uct otx2_cpt_kvf_limits_rsp *) msg;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 cptvf->lfs.kvf_l= imits =3D rsp_limits->kvf_limits;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0case MBOX_MSG_GET_CAPS:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0eng_caps =3D (struc= t otx2_cpt_caps_rsp *)msg;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0memcpy(cptvf->en= g_caps, eng_caps->eng_caps,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 sizeof(cptvf->eng_caps));
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 default:
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(&cptvf-= >pdev->dev, "Unsupported msg %d received.\n",
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 msg->id);
@@ -205,3 +211,23 @@ int otx2_cptvf_send_kvf_limits_msg(struct otx2_cptvf_d= ev *cptvf)

=C2=A0 =C2=A0 =C2=A0 =C2=A0 return otx2_cpt_send_mbox_msg(mbox, pdev);
=C2=A0}
+
+int otx2_cptvf_send_caps_msg(struct otx2_cptvf_dev *cptvf)
+{
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct otx2_mbox *mbox =3D &cptvf->pfvf_= mbox;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct pci_dev *pdev =3D cptvf->pdev;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct mbox_msghdr *req;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0req =3D (struct mbox_msghdr *)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0otx2_mbox_alloc_msg_rsp(mb= ox, 0, sizeof(*req),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sizeof(struct ot= x2_cpt_caps_rsp));
+=C2=A0 =C2=A0 =C2=A0 =C2=A0if (!req) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev_err(&pdev-&= gt;dev, "RVU MBOX failed to get message.\n");
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return -EFAULT;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+=C2=A0 =C2=A0 =C2=A0 =C2=A0req->id =3D MBOX_MSG_GET_CAPS;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0req->sig =3D OTX2_MBOX_REQ_SIG;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0req->pcifunc =3D OTX2_CPT_RVU_PFFUNC(cptvf-&= gt;vf_id, 0);
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return otx2_cpt_send_mbox_msg(mbox, pdev);
+}
diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c b/drivers= /crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c
index 811ded72ce5f..997a2eb60c66 100644
--- a/drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c
+++ b/drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c
@@ -4,9 +4,6 @@
=C2=A0#include "otx2_cptvf.h"
=C2=A0#include "otx2_cpt_common.h"

-/* SG list header size in bytes */
-#define SG_LIST_HDR_SIZE=C2=A0 =C2=A0 =C2=A0 =C2=A08
-
=C2=A0/* Default timeout when waiting for free pending entry in us */
=C2=A0#define CPT_PENTRY_TIMEOUT=C2=A0 =C2=A0 =C2=A01000
=C2=A0#define CPT_PENTRY_STEP=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 50
@@ -26,9 +23,9 @@ static void otx2_cpt_dump_sg_list(struct pci_dev *pdev,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 pr_debug("Gather list size %d\n", req= ->in_cnt);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 for (i =3D 0; i < req->in_cnt; i++) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pr_debug("Buff= er %d size %d, vptr 0x%p, dmaptr 0x%p\n", i,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pr_debug("Buff= er %d size %d, vptr 0x%p, dmaptr 0x%llx\n", i,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0req->in[i].size, req->in[i].vptr,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 (void *) req->in[i].dma_addr);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 req->in[i].dma_addr);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 pr_debug("Buff= er hexdump (%d bytes)\n",
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0req->in[i].size);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 print_hex_dump_debu= g("", DUMP_PREFIX_NONE, 16, 1,
@@ -36,9 +33,9 @@ static void otx2_cpt_dump_sg_list(struct pci_dev *pdev, =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
=C2=A0 =C2=A0 =C2=A0 =C2=A0 pr_debug("Scatter list size %d\n", re= q->out_cnt);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 for (i =3D 0; i < req->out_cnt; i++) { -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pr_debug("Buff= er %d size %d, vptr 0x%p, dmaptr 0x%p\n", i,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pr_debug("Buff= er %d size %d, vptr 0x%p, dmaptr 0x%llx\n", i,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0req->out[i].size, req->out[i].vptr,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 (void *) req->out[i].dma_addr);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 req->out[i].dma_addr);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 pr_debug("Buff= er hexdump (%d bytes)\n", req->out[i].size);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 print_hex_dump_debu= g("", DUMP_PREFIX_NONE, 16, 1,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0req->out[i].v= ptr, req->out[i].size, false);
@@ -84,149 +81,6 @@ static inline void free_pentry(struct otx2_cpt_pending_= entry *pentry)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 pentry->busy =3D false;
=C2=A0}

-static inline int setup_sgio_components(struct pci_dev *pdev,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0struct ot= x2_cpt_buf_ptr *list,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0int buf_c= ount, u8 *buffer)
-{
-=C2=A0 =C2=A0 =C2=A0 =C2=A0struct otx2_cpt_sglist_component *sg_ptr =3D NU= LL;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0int ret =3D 0, i, j;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0int components;
-
-=C2=A0 =C2=A0 =C2=A0 =C2=A0if (unlikely(!list)) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev_err(&pdev-&= gt;dev, "Input list pointer is NULL\n");
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return -EFAULT;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0}
-
-=C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i < buf_count; i++) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (unlikely(!list[= i].vptr))
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0continue;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0list[i].dma_addr = =3D dma_map_single(&pdev->dev, list[i].vptr,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0list[i].size,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0DMA_BIDIRECTIONAL);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (unlikely(dma_ma= pping_error(&pdev->dev, list[i].dma_addr))) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0dev_err(&pdev->dev, "Dma mapping failed\n");
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0ret =3D -EIO;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0goto sg_cleanup;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
-=C2=A0 =C2=A0 =C2=A0 =C2=A0}
-=C2=A0 =C2=A0 =C2=A0 =C2=A0components =3D buf_count / 4;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr =3D (struct otx2_cpt_sglist_component *)= buffer;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i < components; i++) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->len0 =3D= cpu_to_be16(list[i * 4 + 0].size);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->len1 =3D= cpu_to_be16(list[i * 4 + 1].size);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->len2 =3D= cpu_to_be16(list[i * 4 + 2].size);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->len3 =3D= cpu_to_be16(list[i * 4 + 3].size);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->ptr0 =3D= cpu_to_be64(list[i * 4 + 0].dma_addr);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->ptr1 =3D= cpu_to_be64(list[i * 4 + 1].dma_addr);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->ptr2 =3D= cpu_to_be64(list[i * 4 + 2].dma_addr);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->ptr3 =3D= cpu_to_be64(list[i * 4 + 3].dma_addr);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr++;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0}
-=C2=A0 =C2=A0 =C2=A0 =C2=A0components =3D buf_count % 4;
-
-=C2=A0 =C2=A0 =C2=A0 =C2=A0switch (components) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0case 3:
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->len2 =3D= cpu_to_be16(list[i * 4 + 2].size);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->ptr2 =3D= cpu_to_be64(list[i * 4 + 2].dma_addr);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0fallthrough;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0case 2:
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->len1 =3D= cpu_to_be16(list[i * 4 + 1].size);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->ptr1 =3D= cpu_to_be64(list[i * 4 + 1].dma_addr);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0fallthrough;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0case 1:
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->len0 =3D= cpu_to_be16(list[i * 4 + 0].size);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sg_ptr->ptr0 =3D= cpu_to_be64(list[i * 4 + 0].dma_addr);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0default:
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0}
-=C2=A0 =C2=A0 =C2=A0 =C2=A0return ret;
-
-sg_cleanup:
-=C2=A0 =C2=A0 =C2=A0 =C2=A0for (j =3D 0; j < i; j++) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (list[j].dma_add= r) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0dma_unmap_single(&pdev->dev, list[j].dma_addr,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 list[j].= size, DMA_BIDIRECTIONAL);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
-
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0list[j].dma_addr = =3D 0;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0}
-=C2=A0 =C2=A0 =C2=A0 =C2=A0return ret;
-}
-
-static inline struct otx2_cpt_inst_info *info_create(struct pci_dev *pdev,=
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0struct otx2_cpt_req_info *req,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0gfp_t gfp)
-{
-=C2=A0 =C2=A0 =C2=A0 =C2=A0int align =3D OTX2_CPT_DMA_MINALIGN;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0struct otx2_cpt_inst_info *info;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0u32 dlen, align_dlen, info_len;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0u16 g_sz_bytes, s_sz_bytes;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0u32 total_mem_len;
-
-=C2=A0 =C2=A0 =C2=A0 =C2=A0if (unlikely(req->in_cnt > OTX2_CPT_MAX_S= G_IN_CNT ||
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 req-= >out_cnt > OTX2_CPT_MAX_SG_OUT_CNT)) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev_err(&pdev-&= gt;dev, "Error too many sg components\n");
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return NULL;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0}
-
-=C2=A0 =C2=A0 =C2=A0 =C2=A0g_sz_bytes =3D ((req->in_cnt + 3) / 4) *
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0sizeof(struct otx2_cpt_sglist_component);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0s_sz_bytes =3D ((req->out_cnt + 3) / 4) * -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0sizeof(struct otx2_cpt_sglist_component);
-
-=C2=A0 =C2=A0 =C2=A0 =C2=A0dlen =3D g_sz_bytes + s_sz_bytes + SG_LIST_HDR_= SIZE;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0align_dlen =3D ALIGN(dlen, align);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0info_len =3D ALIGN(sizeof(*info), align);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0total_mem_len =3D align_dlen + info_len + sizeo= f(union otx2_cpt_res_s);
-
-=C2=A0 =C2=A0 =C2=A0 =C2=A0info =3D kzalloc(total_mem_len, gfp);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0if (unlikely(!info))
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return NULL;
-
-=C2=A0 =C2=A0 =C2=A0 =C2=A0info->dlen =3D dlen;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0info->in_buffer =3D (u8 *)info + info_len; -
-=C2=A0 =C2=A0 =C2=A0 =C2=A0((u16 *)info->in_buffer)[0] =3D req->out_= cnt;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0((u16 *)info->in_buffer)[1] =3D req->in_c= nt;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0((u16 *)info->in_buffer)[2] =3D 0;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0((u16 *)info->in_buffer)[3] =3D 0;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_to_be64s((u64 *)info->in_buffer);
-
-=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Setup gather (input) components */
-=C2=A0 =C2=A0 =C2=A0 =C2=A0if (setup_sgio_components(pdev, req->in, req= ->in_cnt,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&info->in_buffer[8])) {=
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev_err(&pdev-&= gt;dev, "Failed to setup gather list\n");
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto destroy_info;<= br> -=C2=A0 =C2=A0 =C2=A0 =C2=A0}
-
-=C2=A0 =C2=A0 =C2=A0 =C2=A0if (setup_sgio_components(pdev, req->out, re= q->out_cnt,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&info->in_buffer[8 + g_= sz_bytes])) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev_err(&pdev-&= gt;dev, "Failed to setup scatter list\n");
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto destroy_info;<= br> -=C2=A0 =C2=A0 =C2=A0 =C2=A0}
-
-=C2=A0 =C2=A0 =C2=A0 =C2=A0info->dma_len =3D total_mem_len - info_len;<= br> -=C2=A0 =C2=A0 =C2=A0 =C2=A0info->dptr_baddr =3D dma_map_single(&pde= v->dev, info->in_buffer,
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0in= fo->dma_len, DMA_BIDIRECTIONAL);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0if (unlikely(dma_mapping_error(&pdev->de= v, info->dptr_baddr))) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev_err(&pdev-&= gt;dev, "DMA Mapping failed for cpt req\n");
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto destroy_info;<= br> -=C2=A0 =C2=A0 =C2=A0 =C2=A0}
-=C2=A0 =C2=A0 =C2=A0 =C2=A0/*
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 * Get buffer for union otx2_cpt_res_s response=
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 * structure and its physical address
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 */
-=C2=A0 =C2=A0 =C2=A0 =C2=A0info->completion_addr =3D info->in_buffer= + align_dlen;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0info->comp_baddr =3D info->dptr_baddr + a= lign_dlen;
-
-=C2=A0 =C2=A0 =C2=A0 =C2=A0return info;
-
-destroy_info:
-=C2=A0 =C2=A0 =C2=A0 =C2=A0otx2_cpt_info_destroy(pdev, info);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0return NULL;
-}
-
=C2=A0static int process_request(struct pci_dev *pdev, struct otx2_cpt_req_= info *req,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0struct otx2_cpt_pending_queue *pqueue,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0struct otx2_cptlf_info *lf)
@@ -247,7 +101,7 @@ static int process_request(struct pci_dev *pdev, struct= otx2_cpt_req_info *req,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (unlikely(!otx2_cptlf_started(lf->lfs)))<= br> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return -ENODEV;

-=C2=A0 =C2=A0 =C2=A0 =C2=A0info =3D info_create(pdev, req, gfp);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0info =3D lf->lfs->ops->cpt_sg_info_cre= ate(pdev, req, gfp);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (unlikely(!info)) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(&pdev-&= gt;dev, "Setting up cpt inst info failed");
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return -ENOMEM;
@@ -303,8 +157,8 @@ static int process_request(struct pci_dev *pdev, struct= otx2_cpt_req_info *req,

=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* 64-bit swap for microcode data reads, not ne= eded for addresses*/
=C2=A0 =C2=A0 =C2=A0 =C2=A0 cpu_to_be64s(&iq_cmd.cmd.u);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0iq_cmd.dptr =3D info->dptr_baddr;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0iq_cmd.rptr =3D 0;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0iq_cmd.dptr =3D info->dptr_baddr | info->= gthr_sz << 60;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0iq_cmd.rptr =3D info->rptr_baddr | info->= sctr_sz << 60;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 iq_cmd.cptr.u =3D 0;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 iq_cmd.cptr.s.grp =3D ctrl->s.grp;

--
2.25.1




--
Regards,
Kalesh A P
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