Received-SPF: pass (google.com: domain of linux-crypto+bounces-1074-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249;
Precedence: bulk
Mime-Version: 1.0
Content-Transfer-Encoding: quoted-printable
Content-Type: text/plain; charset=UTF-8
Date: Thu, 28 Dec 2023 15:29:56 +0100
Message-Id: <CY01EKQVWE36.B9X5TDXAREPF@fairphone.com>
Cc: <neil.armstrong@linaro.org>, <konrad.dybcio@linaro.org>,
 <agross@kernel.org>, <andersson@kernel.org>, <conor+dt@kernel.org>,
 <davem@davemloft.net>, <devicetree@vger.kernel.org>,
 <herbert@gondor.apana.org.au>, <krzysztof.kozlowski+dt@linaro.org>,
 <linux-arm-msm@vger.kernel.org>, <linux-crypto@vger.kernel.org>,
 <linux-kernel@vger.kernel.org>, <marijn.suijten@somainline.org>,
 <robh+dt@kernel.org>, <vkoul@kernel.org>,
 <cros-qcom-dts-watchers@chromium.org>
Subject: Re: [PATCH V3 2/2] arm64: dts: qcom: sc7280: add QCrypto nodes
From: "Luca Weiss" <luca.weiss@fairphone.com>
To: "Om Prakash Singh" <quic_omprsing@quicinc.com>
References: <20231214103600.2613988-1-quic_omprsing@quicinc.com>
 <20231214103600.2613988-3-quic_omprsing@quicinc.com>
In-Reply-To: <20231214103600.2613988-3-quic_omprsing@quicinc.com>

On Thu Dec 14, 2023 at 11:36 AM CET, Om Prakash Singh wrote:
> Add the QCE and Crypto BAM DMA nodes.
>
> Signed-off-by: Om Prakash Singh <quic_omprsing@quicinc.com>
> ---
>
> Changes in V3:
>   - V2 patch was sent without actual modification. Resending the patch wi=
th modified file.
>
> Changes in V2:
>   - Update DT node sequence as per register ascending order.
>   - Fix DT node properties as per convention.
>
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/q=
com/sc7280.dtsi
> index 66f1eb83cca7..b819724c1255 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -2233,6 +2233,28 @@ pcie1_phy: phy@1c0e000 {
>  			status =3D "disabled";
>  		};
> =20
> +		cryptobam: dma-controller@1dc4000 {
> +			compatible =3D "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
> +			reg =3D <0x0 0x01dc4000 0x0 0x28000>;
> +			interrupts =3D <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
> +			#dma-cells =3D <1>;
> +			iommus =3D <&apps_smmu 0x4e4 0x0011>,
> +				 <&apps_smmu 0x4e6 0x0011>;
> +			qcom,ee =3D <0>;
> +			qcom,controlled-remotely;
> +		};

Hi,

Unfortunately I seem to have boot failure / device crash with cryptobam
enabled on my qcm6490-fairphone-fp5. Are you aware of any firmware
differences that could cause this with QCM6490 LA firmware?

Looking at downstream msm-5.4 dmesg I do see this BAM being used so it
should generally be accessible from Linux.

[    5.217214] qce 1de0000.qcedev: Adding to iommu group 18
[    5.223741] QCE50: __qce_get_device_tree_data: CE operating frequency is=
 not defined, setting to default 100MHZ
[    5.234986] qce 1de0000.qcedev: QTI Crypto 5.6.0 device found @0x1de0000
[    5.242981] sps_register_bam_device: sps:BAM 0x0000000001dc4000 is regis=
tered
[    5.251124] sps_bam_enable: sps:BAM 0x0000000001dc4000 (va:0x000000001db=
63156) enabled: ver:0x27, number of pipes:16
[    5.262783] QCE50: qce_sps_init:  QTI MSM CE-BAM at 0x0000000001dc4000 i=
rq 9
[    5.271820] qce 1de0000.qcedev:qcom_cedev_ns_cb: Adding to iommu group 1=
9
[    5.281083] qce 1de0000.qcedev:qcom_cedev_s_cb: Adding to iommu group 20
[    5.289376] qcrypto 1de0000.qcrypto: Adding to iommu group 21
[    5.296326] QCE50: __qce_get_device_tree_data: CE operating frequency is=
 not defined, setting to default 100MHZ
[    5.307675] qcrypto 1de0000.qcrypto: QTI Crypto 5.6.0 device found @0x1d=
e0000
[    5.315867] QCE50: qce_sps_init:  QTI MSM CE-BAM at 0x0000000001dc4000 i=
rq 9

Any idea?

Regards
Luca

> +
> +		crypto: crypto@1dfa000 {
> +			compatible =3D "qcom,sc7280-qce", "qcom,sm8150-qce", "qcom,qce";
> +			reg =3D <0x0 0x01dfa000 0x0 0x6000>;
> +			dmas =3D <&cryptobam 4>, <&cryptobam 5>;
> +			dma-names =3D "rx", "tx";
> +			iommus =3D <&apps_smmu 0x4e4 0x0011>,
> +				 <&apps_smmu 0x4e4 0x0011>;
> +			interconnects =3D <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>=
;
> +			interconnect-names =3D "memory";
> +		};
> +
>  		ipa: ipa@1e40000 {
>  			compatible =3D "qcom,sc7280-ipa";
> =20