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Thu, 1 Feb 2024 10:37:40 +0800 Received: from [10.32.57.248] (10.32.57.248) by zxbjmbx1.zhaoxin.com (10.29.252.163) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 1 Feb 2024 10:37:37 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.163 Message-ID: <858b8c95-a0b7-4085-9ae4-824bec4d3c67@zhaoxin.com> X-Barracuda-RBL-Trusted-Forwarder: 10.32.57.248 Date: Thu, 1 Feb 2024 10:37:36 +0800 Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] crypto: padlock-sha: Matches CPU with Family with 6 explicitly Content-Language: en-US X-ASG-Orig-Subj: Re: [PATCH v2 1/3] crypto: padlock-sha: Matches CPU with Family with 6 explicitly To: Dave Hansen , , , , , , , , , , , , , , , , , , , CC: , , , References: <20240123022852.2475-1-TonyWWang-oc@zhaoxin.com> <20240123022852.2475-2-TonyWWang-oc@zhaoxin.com> <54d4fe7f-2e36-4bb3-8b51-4a68510010d5@intel.com> <40e74749-fa9d-4089-ae23-e9aefdd3549f@zhaoxin.com> <85dd3df3-9c0e-45e2-af8d-50dbc0cf40c8@intel.com> From: Tony W Wang-oc In-Reply-To: <85dd3df3-9c0e-45e2-af8d-50dbc0cf40c8@intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: ZXSHCAS1.zhaoxin.com (10.28.252.161) To zxbjmbx1.zhaoxin.com (10.29.252.163) X-Barracuda-Connect: ZXSHMBX1.zhaoxin.com[10.28.252.163] X-Barracuda-Start-Time: 1706755060 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.36:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 1244 X-Barracuda-BRTS-Status: 0 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.120217 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- On 2024/1/31 23:33, Dave Hansen wrote: > > [这封邮件来自外部发件人 谨防风险] > > On 1/31/24 01:45, Tony W Wang-oc wrote: >>>> static const struct x86_cpu_id padlock_sha_ids[] = { >>>> - X86_MATCH_FEATURE(X86_FEATURE_PHE, NULL), >>>> + X86_MATCH_VENDOR_FAM_FEATURE(CENTAUR, 6, X86_FEATURE_PHE, NULL), >>>> {} >>>> }; >>> Logically, this is saying that there are non-CENTAUR or non-family-6 >>> CPUs that set X86_FEATURE_PHE, but don't support X86_FEATURE_PHE. Is >>> that the case? >> Not exactly. >> >> Zhaoxin CPU supports X86_FEATURE_PHE and X86_FEATURE_PHE2. >> >> We expect the Zhaoxin CPU to use the zhaoxin_sha driver introduced in >> the third patch of this patch set. >> >> Without this patch Zhaoxin CPU will also match the padlock-sha driver too. > I honestly have no idea what this is saying. > > Could you try again, please? Sorry. It should be said that there are non-CENTAUR or non-family-6 CPUs that set X86_FEATURE_PHE, and also set the new X86_FEATURE_PHE2.  For these CPUs, we expect to use a new driver that supports both X86_FEATURE_PHE and X86_FEATURE_PHE2. So we make the driver padlock-sha to matches CENTAUR Family-6 CPU explicitly.