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From: Alexey Romanov <avromanov@salutedevices.com>
To: Jerome Brunet <jbrunet@baylibre.com>
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Subject: Re: [PATCH v5 03/21] drivers: crypto: meson: make CLK controller
 optional
Thread-Topic: [PATCH v5 03/21] drivers: crypto: meson: make CLK controller
 optional
Thread-Index: AQHaa9yRWJ/V2yQniEGD1LRIiVhVdrEizjUAgASdYgA=
Date: Mon, 4 Mar 2024 13:49:46 +0000
Message-ID: <20240304134923.hk5xp5rs3itgw3pk@cab-wsm-0029881.sigma.sbrf.ru>
References: <20240301132936.621238-1-avromanov@salutedevices.com>
 <20240301132936.621238-4-avromanov@salutedevices.com>
 <1jwmqmrmva.fsf@starbuckisacylon.baylibre.com>
In-Reply-To: <1jwmqmrmva.fsf@starbuckisacylon.baylibre.com>
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Hello Jerome,

On Fri, Mar 01, 2024 at 04:21:20PM +0100, Jerome Brunet wrote:
>=20
> On Fri 01 Mar 2024 at 16:29, Alexey Romanov <avromanov@salutedevices.com>=
 wrote:
>=20
> > Amlogic crypto IP doesn't take a clock input on some
> > SoCs: AXG / A1 / S4 / G12. So make it optional.
> >
>=20
> I commented this patch on v2 and the comment keep on being un-addressed.
>=20
> The SoC either:
> * has a clock that is required for the IP to work
> * Or does not
>=20
> It is not something you are free to provide or not.
>=20
> For the record, I find very hard believe that some SoC would have clock,
> and other would not, for the same HW.
>=20
> Isn't it more likely that the clock just happens to be left enabled by
> the bootloader on some SoC and it conviently allows to ignore it ?


S905X and newer SoC's uses DMA engine for crypto HW and they
don't required clock input to work. Clock input is needed for
blkmv engine.

Therefore, I'm not sure that it is needed for GXL too (and the second
interrupt line). I tested it on vim1 board witouht them and everything
works correctly.

>=20
> > Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
> > ---
> >  drivers/crypto/amlogic/amlogic-gxl-core.c | 14 +++-----------
> >  1 file changed, 3 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/crypto/amlogic/amlogic-gxl-core.c b/drivers/crypto=
/amlogic/amlogic-gxl-core.c
> > index e9e733ed98e0..a3a69a59f476 100644
> > --- a/drivers/crypto/amlogic/amlogic-gxl-core.c
> > +++ b/drivers/crypto/amlogic/amlogic-gxl-core.c
> > @@ -269,16 +269,11 @@ static int meson_crypto_probe(struct platform_dev=
ice *pdev)
> >  		dev_err(&pdev->dev, "Cannot request MMIO err=3D%d\n", err);
> >  		return err;
> >  	}
> > -	mc->busclk =3D devm_clk_get(&pdev->dev, "blkmv");
> > +
> > +	mc->busclk =3D devm_clk_get_optional_enabled(&pdev->dev, "blkmv");
> >  	if (IS_ERR(mc->busclk)) {
> >  		err =3D PTR_ERR(mc->busclk);
> > -		dev_err(&pdev->dev, "Cannot get core clock err=3D%d\n", err);
> > -		return err;
> > -	}
> > -
> > -	err =3D clk_prepare_enable(mc->busclk);
> > -	if (err !=3D 0) {
> > -		dev_err(&pdev->dev, "Cannot prepare_enable busclk\n");
> > +		dev_err(&pdev->dev, "Cannot get and enable core clock err=3D%d\n", e=
rr);
> >  		return err;
> >  	}
> > =20
> > @@ -306,7 +301,6 @@ static int meson_crypto_probe(struct platform_devic=
e *pdev)
> >  	meson_unregister_algs(mc);
> >  error_flow:
> >  	meson_free_chanlist(mc, mc->flow_cnt - 1);
> > -	clk_disable_unprepare(mc->busclk);
> >  	return err;
> >  }
> > =20
> > @@ -321,8 +315,6 @@ static void meson_crypto_remove(struct platform_dev=
ice *pdev)
> >  	meson_unregister_algs(mc);
> > =20
> >  	meson_free_chanlist(mc, mc->flow_cnt - 1);
> > -
> > -	clk_disable_unprepare(mc->busclk);
> >  }
> > =20
> >  static const struct meson_pdata meson_gxl_pdata =3D {
>=20
>=20
> --=20
> Jerome

--=20
Thank you,
Alexey=